linux-kernel - Re: Assignment of GDT entries

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Date:	Wed, 13 Sep 2006 15:55:00 -0400
From:	"linux-os \(Dick Johnson\)" <linux-os@...logic.com>
To:	"Jeremy Fitzhardinge" <jeremy@...p.org>
Cc:	"Linus Torvalds" <torvalds@...l.org>,
	"Ingo Molnar" <mingo@...e.hu>, "Andi Kleen" <ak@...e.de>,
	"Eric W. Biederman" <ebiederm@...ssion.com>,
	"Arjan van de Ven" <arjan@...radead.org>,
	"Zachary Amsden" <zach@...are.com>,
	"Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>,
	"Michael A Fetterman" <Michael.Fetterman@...cam.ac.uk>
Subject: Re: Assignment of GDT entries

On Wed, 13 Sep 2006, Jeremy Fitzhardinge wrote:

> What's the rationale for the current assignment of GDT entries?  In
> particular, this section:
>
> *   0 - null
> *   1 - reserved
> *   2 - reserved
> *   3 - reserved
> *
> *   4 - unused			<==== new cacheline
> *   5 - unused
> *
> *  ------- start of TLS (Thread-Local Storage) segments:
> *
> *   6 - TLS segment #1			[ glibc's TLS segment ]
> *   7 - TLS segment #2			[ Wine's %fs Win32 segment ]
> *   8 - TLS segment #3
> *   9 - reserved
> *  10 - reserved
> *  11 - reserved
>
>
> What are entries 1-3 and 9-11 reserved for?  Must they be unused for
> some reason, or is there some proposed use that has not been impemented yet?
>

In the ix86, the first descriptor in the GDT is not used. The are
TWO 32-bits words for each GDT entry. The GDT numbers are the offset from
the first, so they are numbered as offsets, there are multiplied by
8, the size of a GDT, by the processor when they are used to set segment
registers. This table is only accessed by the CPU when the LGDT
instruction in executed. When a segment register is set, the invisible
part of the segment, the top 16 bits, contains the information extracted
from the GDT, so no further access is necessary. This means that
it has nothing to do with cache-lines.

The entries 1 through 3 are used during the boot sequence, see
setup.S, search for "gdt" around line 983.

> Also, is there a particular reason kernel GDT entries start at 12?
> Would there be a problem in using either 4 or 5 for a kernel GDT descriptor?
>
> I'm asking because I'd like to use one of these entries for the PDA
> descriptor, so that it is on the same cache line as the TLS
> descriptors.  That way, the entry/exit segment register reloads would
> still only need to touch two GDT cache lines.  Would there be a real
> problem in doing this?
>

You can add other GDT entries up to 8192 if you want. If you set the
base, limit, type, etc., to something that's different than the
kernel DS, SS, CS, etc., then you need to reload the segment registers
and if the base is different, the code offset will be WRONG so you
will need to tell the linker the new relocation information.

I can't imagine a reason why you'd want to do this.

> Thanks,
>    J
>

Cheers,
Dick Johnson
Penguin : Linux version 2.6.16.24 on an i686 machine (5592.66 BogoMips).
New book: http://www.AbominableFirebug.com/
_
..

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