lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Sat, 28 Oct 2006 02:46:41 -0700 From: Andi Kleen <ak@...e.de> To: thockin@...kin.org Cc: Andrew Morton <akpm@...l.org>, Sergio Monteiro Basto <sergio@...giomb.no-ip.org>, Lee Revell <rlrevell@...-job.com>, Chris Friesen <cfriesen@...tel.com>, linux-kernel <linux-kernel@...r.kernel.org>, john stultz <johnstul@...ibm.com> Subject: Re: AMD X2 unsynced TSC fix? > Nothing at all, or just the the low few bits are writeable? I had heard, > but never seen that some Intel CPUs only allowed 16 bits of writable bits > in the TSC MSR. I also heard of, but never saw, CPUs that cleared the TSC > to 0 on a write! Normally on Intel you can only write the first 32bits -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists