linux-kernel - Re: cpufreq longhaul locks up

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Sat, 5 May 2007 19:38:15 +0200 (MEST)
From:	Jan Engelhardt <jengelh@...ux01.gwdg.de>
To:	Rafał Bilski <rafalbilski@...eria.pl>
cc:	David Johnson <dj@...id-web.co.uk>, cpufreq@...ts.linux.org.uk,
	linux-kernel@...r.kernel.org
Subject: Re: cpufreq longhaul locks up


On May 5 2007 16:10, Rafał Bilski wrote:
>
>>> Can You send output of x86info program and output of 
>> 
>> Where do I find this?
>
>http://www.codemonkey.org.uk/projects/x86info/
>It needs msr device support in kernel.

I just wonder why x86info says I have a C5XL while `modprobe longhaul`
says it is a C5P.


cn:/dev/shm # ./x86info -v -v
x86info v1.20.  Dave Jones 2001-2006
Feedback to <davej@...hat.com>.

Found 1 CPU
--------------------------------------------------------------------------
Family: 6 Model: 9 Stepping: 8
CPU Model : VIA C3 (Nehemiah) [C5XL]
Feature flags:
        Onboard FPU
        Virtual Mode Extensions
        Debugging Extensions
        Page Size Extensions
        Time Stamp Counter
        Model-Specific Registers
        CMPXCHG8 instruction
        Memory Type Range Registers
        Page Global Enable
        CMOV instruction
        Page Attribute Table
        MMX support
        FXSAVE and FXRESTORE instructions
        SSE support

Extended feature flags:
 [0] RNGp RNGe [4] ACEp ACEe
Cache info
 L1 Instruction cache: 64KB, 4-way associative, 1 lines per tag, line size=32
bytes.
 L1 Data cache: 64KB 4-way associative, 1 lines per tag, line size=32 bytes.
 L2 (on CPU) cache: 64KB 8-way associative, 1 lines per tag, line size=32
bytes.
TLB info
 Instruction TLB: 8-way associative. 128 entries.
 Data TLB: 8-way associative. 128 entries.

(Without -v it's:)
Feature flags:
 fpu vme de pse tsc msr cx8 mtrr pge cmov pat mmx fxsr sse


cn:/dev/shm # cat /proc/cpuinfo 
processor       : 0
vendor_id       : CentaurHauls
cpu family      : 6
model           : 9
model name      : VIA Nehemiah
stepping        : 8
cpu MHz         : 731.000
cache size      : 64 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr cx8 mtrr pge cmov pat mmx fxsr sse up
rng rng_en ace ace_en
bogomips        : 1468.17
clflush size    : 32


And the BIOS announces it as a "Via Eden ESP 6000" (as does the manufacturer).



Jan
-- 
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/