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Date: Sat, 26 May 2007 19:49:45 -0600 From: Grant Grundler <grundler@...isc-linux.org> To: Manu Abraham <abraham.manu@...il.com> Cc: linux-pci@...ey.karlin.mff.cuni.cz, linux-kernel@...r.kernel.org Subject: Re: PCIE On Sun, May 27, 2007 at 05:01:02AM +0400, Manu Abraham wrote: > David Miller wrote: > > True, on sparc64 PCI-E controllers, for example, the MSI vector is > > received by the PCI-E host controller, and the host controller turns > > this into a cpu format interrupt packet for the system bus. > > Err .. why would a PCIe controller be CPU specific ? Looking at Figure > 1-6 of the spec, i think it should be CPU independent ? To be pedantic, the PCIe controller isn't really CPU specific. It's host bus specific. ie the PCI-e controller is a bridge between whatever chipset defines the "cache coherency domain" and the PCI-e devices. > Excuse me for my ignorance, just that my head has begun to reel after > reading through PCIe 1.0 and the device specs, still being inconclusive > how to proceed. no problem...I suspect you need to figure out why DTL-MMIO isn't working. I have never touched DTL and can't be of much help with that. hth, grant - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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