linux-kernel - Re: [Fwd: Re: [PATCH 0/5]PCI: x86 MMCONFIG]

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Date:	Thu, 20 Dec 2007 20:35:25 -0500
From:	Tony Camuso <tcamuso@...hat.com>
To:	Robert Hancock <hancockr@...w.ca>
CC:	Greg KH <gregkh@...e.de>, linux-kernel@...r.kernel.org,
	linux-pci@...ey.karlin.mff.cuni.cz,
	"Chumbalkar, Nagananda" <Nagananda.Chumbalkar@...com>,
	Prarit Bhargava <prarit@...hat.com>, bnagendr@...hat.com
Subject: Re: [Fwd: Re: [PATCH 0/5]PCI: x86 MMCONFIG]

Robert Hancock wrote:

> First off, I would like to see confirmation from the horses's mouths 
> here (namely AMD, ServerWorks/Broadcom, and whoever else) that there is 
> no other way to get around this problem than disabling MMCONFIG for 
> accesses behind those chips.
> 

I happen to have this one stored in my desktop.

 From AMD-8132TM HyperTransportTM
      PCI-X®2.0 Tunnel
       Revision Guide

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30801.pdf

79 AMD-8132TM Tunnel Lacks Extended Configuration
         Space Memory-Mapped I/O Base Address Register

Description

Current AMD processors do not natively support PCI-defined extended configuration space. A memory
mapped I/O base address register (MMIO BAR) is required in chipset devices to support extended
configuration space. The AMD-8132 does not have this MMIO BAR.
Potential Effect On System

The AMD-8132 is a PCI-X® Mode 2 capable device and requires the MMIO BAR to support extended
configuration space. Using a device which does have this MMIO BAR and an AMD-8132 on the same
HyperTransportTM link of the processor may cause firmware/software problems.

The base configuration space of the AMD-8132 and PCI(-X) devices attached to it are accessible using only
the mechanism defined in PCI 2.3. Registers of PCI-X Mode 2 devices attached to the AMD-8132 in the
extended configuration space are not accessible. The AMD-8132 has no registers in the extended
configuration space.

Suggested Workaround

It is strongly recommended that system designers do not connect the AMD-8132 and devices that use extended
configuration space MMIO BARs (ex: HyperTransport-to-PCI Express® bridges) to the same processor
HyperTransport link.

Fix Planned
No

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