linux-kernel - Re: MMIO and gcc re-ordering issue

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Date:	Fri, 30 May 2008 13:56:02 +1000
From:	Paul Mackerras <paulus@...ba.org>
To:	Trent Piepho <tpiepho@...escale.com>
Cc:	Roland Dreier <rdreier@...co.com>, Jes Sorensen <jes@....com>,
	benh@...nel.crashing.org, Arjan van de Ven <arjan@...radead.org>,
	linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
	linuxppc-dev@...abs.org, scottwood@...escale.com,
	torvalds@...ux-foundation.org, David Miller <davem@...emloft.net>,
	alan@...rguk.ukuu.org.uk
Subject: Re: MMIO and gcc re-ordering issue

Trent Piepho writes:

> On Thu, 29 May 2008, Roland Dreier wrote:
> > > The problem is that your two writel's, despite being both issued on
> > > cpu X, due to the spin lock, in your example, can end up with the
> > > first one going through NR 1 and the second one going through NR 2. If
> > > there's contention on NR 1, the write going via NR 2 may hit the PCI
> > > bridge prior to the one going via NR 1.
> >
> > Really??  I can't see how you can expect any drivers to work reliably if
> > simple code like
> >
> > 	writel(reg1);
> > 	writel(reg2);
> >
> > might end up with the write to reg2 hitting the device before the write
> > to reg1.  Almost all MMIO stuff has ordering requirements and will
> 
> This is how powerpc is natively (the linux accessors have extra ordering to
> not allow this of course), and there are non-Linux drivers that are written
> for this ordering model.

In fact stores to non-cacheable locations have to be kept in order,
according to the Power architecture.  But you're correct in that
non-cacheable loads can in principle be reordered w.r.t. each other
and to stores.

> I think what makes altix so hard is that writes to the _same_ register may be
> be re-ordered.  Re-ordering writes to the same address is much less common
> than allowing writes to different addresses to be re-ordered.

Indeed.

Paul.
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