linux-kernel - RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part

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Date:	Sat, 4 Oct 2008 07:17:53 -0700
From:	"Yu, Fenghua" <fenghua.yu@...el.com>
To:	David Woodhouse <dwmw2@...radead.org>
CC:	Bjorn Helgaas <bjorn.helgaas@...com>,
	"Luck, Tony" <tony.luck@...el.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Ingo Molnar <mingo@...e.hu>, Avi Kivity <avi@...hat.com>,
	Stephen Rothwell <sfr@...b.auug.org.au>,
	Andrew Morton <akpm@...ux-foundation.org>,
	LKML <linux-kernel@...r.kernel.org>,
	"linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>
Subject: RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel
	IOMMU: IA64 Specific Part

>> VT-d hardware supports both non cache coherency and cache coherency by
>> bit Coherency in Extended Capabilities Register.
>
>But is the version without the cache coherency actually going to be
>_seen_ on IA64?
>
Currently there is only one IA64 platform CraterLake supporting VT-d. Its BIOS sets cache coherency bit. But since there is no architecture spec saying cache coherency is required for all ia64 platforms, non cache coherency could be seen in future platforms having VT-d. And one VT-d architect explicitly tell me that ia64 Linux IOMMU needs to deal with non cache coherency case and flush cache line for non cache coherency case (just like x86-64 is doing).

>> Could you please point me to the doc that explicitly says that
>> architecturally ia64 doesn't need cache flush?
>
>For safety, we can always make the driver just refuse to initialise on
>IA64 if the cache coherency bit isn't set.

The current patch set works just fine for both cache coherency and non cache coherency. We don't need to abandon non cache coherency support on ia64 unless there is explicit spec claiming that non cache coherency is a requirement on all ia64 platforms.

Thanks.

-Fenghua
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