linux-kernel - Re: libata, devm

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 21 Jan 2009 15:16:18 +1100
From:	Michael Ellerman <michael@...erman.id.au>
To:	Grant Grundler <grundler@...gle.com>
Cc:	Mark Lord <liml@....ca>, Daniel Barkalow <barkalow@...ervon.org>,
	IDE/ATA development list <linux-ide@...r.kernel.org>,
	Linux Kernel <linux-kernel@...r.kernel.org>,
	Tejun Heo <htejun@...il.com>, Jeff Garzik <jgarzik@...ox.com>,
	linux-pci@...r.kernel.org
Subject: Re: libata, devm_*, and MSI ?

On Tue, 2009-01-20 at 20:02 -0800, Grant Grundler wrote:
> On Tue, Jan 20, 2009 at 7:39 PM, Mark Lord <liml@....ca> wrote:
> ...
> > Next.. who knows something about debugging MSI across PCI bridges ?
> > I've got a 64-bit box here, PCIe near the core, but with full PCI-X
> > slots on the far side of two bridges.
> >
> > The kernel happily allows my driver to setup MSI, but the interrupts
> > never arrive.  So something somewhere in between is either
> >
> > (1) not set up or quirked quite right, or
> > (2) one of the bridges won't pass MSI and we don't detect that.
> >
> > I'll poke more at it later and post some info, if somebody out there
> > knows enough about this kind of thing to provide some basic hints.
> 
> 
> Basic Hints:
> 1) post lspci -v output to verify device (and bridges) is programmed correctly.
> 2) look for chipset quirks that disable global msi

The kernel shouldn't let you enable MSI if that's the case, ie.
pci_enable_msi() should fail.

It might still be worth looking at the quirks though, in case there's
one for a previous revision of your bridge or something.

> 3) Make sure MMIO ranges for 0xfee00000 are routed to local APIC
>    ie each bridge needs to route that address somehow (negative decode
> is common for upstream).
> 4) manually trigger the MSI by doing a MMIO write to the correct
> 0xfee00000 address with the assigned vector in order to see if your
> interrupt handler gets called.

And can you plug something directly into the PCIe bus? If so does MSI
work on that?

cheers

-- 
Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person

Download attachment "signature.asc" of type "application/pgp-signature" (198 bytes)