linux-kernel - Re: [Xen-devel] [PATCH 10/24] xen: mask XSAVE from cpuid

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Date:	Tue, 17 Mar 2009 00:59:20 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	"Jan Beulich" <jbeulich@...ell.com>
Cc:	"Arjan van de Ven" <arjan@...radead.org>,
	"Jeremy Fitzhardinge" <jeremy.fitzhardinge@...rix.com>,
	"Jeremy Fitzhardinge" <jeremy@...p.org>,
	"the arch/x86 maintainers" <x86@...nel.org>,
	"Xen-devel" <xen-devel@...ts.xensource.com>,
	"Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>,
	"H. Peter Anvin" <hpa@...or.com>
Subject: Re: [Xen-devel] [PATCH 10/24] xen: mask XSAVE from cpuid

"Jan Beulich" <jbeulich@...ell.com> writes:

>>>> Arjan van de Ven <arjan@...radead.org> 16.03.09 01:09 >>>
>>Well.. pretty much all new instructions need Xen modifications due to
>>the need to be emulate to deal with traps/vmexits/etc right? 
>>So I don't quite see many cpuid bits that would NOT involve some Xen
>>modification or another ;)
>
> No, new (user-mode accessible) instructions represent precisely the kind
> of extension that do not require hypervisor (or OS) awareness (see SSE2
> etc, AES, FMA). New registers otoh are examples of where awareness is
> needed (SSE, AVX), as would be new privileged instructions.

Whey would another hypothetical FP register extension need Xen support
once it gets proper XSAVE support? I can't think of a reason why
(assuming XSAVE support) it would need to know of a new kind of
FP register or similar. They very likely won't appear in any 
instructions that need mmio. Or are you worried about the real
mode emulator?

-Andi

-- 
ak@...ux.intel.com -- Speaking for myself only.
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