linux-kernel - Re: [PATCH 0/2] [GIT PULL] tracing: various bug fixes

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Date:	Thu, 23 Apr 2009 11:02:38 -0700
From:	Chris Wright <chrisw@...s-sol.org>
To:	Chris Wright <chrisw@...s-sol.org>
Cc:	Jeremy Fitzhardinge <jeremy@...p.org>,
	Steven Rostedt <rostedt@...dmis.org>,
	Ingo Molnar <mingo@...e.hu>,
	Frédéric Weisbecker <fweisbec@...il.com>,
	LKML <linux-kernel@...r.kernel.org>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Glauber de Oliveira Costa <gcosta@...hat.com>,
	Rusty Russell <rusty@...tcorp.com.au>,
	Pekka Enberg <penberg@...helsinki.fi>
Subject: Re: [PATCH 0/2] [GIT PULL] tracing: various bug fixes

* Chris Wright (chrisw@...s-sol.org) wrote:
> * Jeremy Fitzhardinge (jeremy@...p.org) wrote:
> > OK, the good news is that its not a callee-save calling convention  
> > problem, which is what I feared.  But it does sound pretty awkward to  
> > fix.  Does __native_flush_tlb_global() have to use  
> > raw_local_irq_save/restore?
> 
> Vaguely related...makes sense to do native_(read/write)_cr4 since it's
> the native tlb flushing implementation, no?
> 
> looks ok from inspection, not tested yet...

BTW, Steve, does that fix it for you?  Sure makes the code cleaner:

 410:   0f 20 e2                mov    %cr4,%rdx
 413:   48 89 d0                mov    %rdx,%rax
 416:   24 7f                   and    $0x7f,%al
 418:   0f 22 e0                mov    %rax,%cr4
 41b:   0f 22 e2                mov    %rdx,%cr4

thanks,
-chris

> Subject: [PATCH] x86: use native register access for native tlb flushing
> 
> currently these are paravirtulaized, doesn't appear any callers rely on
> this (no pv_ops backends are using native_tlb and overriding cr3/4
> access).
> 
> Signed-off-by: Chris Wright <chrisw@...s-sol.org>
> ---
>  arch/x86/include/asm/tlbflush.h |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
> index 16a5c84..a5ecc9c 100644
> --- a/arch/x86/include/asm/tlbflush.h
> +++ b/arch/x86/include/asm/tlbflush.h
> @@ -17,7 +17,7 @@
>  
>  static inline void __native_flush_tlb(void)
>  {
> -	write_cr3(read_cr3());
> +	native_write_cr3(native_read_cr3());
>  }
>  
>  static inline void __native_flush_tlb_global(void)
> @@ -32,11 +32,11 @@ static inline void __native_flush_tlb_global(void)
>  	 */
>  	raw_local_irq_save(flags);
>  
> -	cr4 = read_cr4();
> +	cr4 = native_read_cr4();
>  	/* clear PGE */
> -	write_cr4(cr4 & ~X86_CR4_PGE);
> +	native_write_cr4(cr4 & ~X86_CR4_PGE);
>  	/* write old PGE again and flush TLBs */
> -	write_cr4(cr4);
> +	native_write_cr4(cr4);
>  
>  	raw_local_irq_restore(flags);
>  }
--
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