linux-kernel - [tip:tracing/core] x86: use native register access for native tlb flushing

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Date:	Wed, 29 Apr 2009 06:16:26 GMT
From:	tip-bot for Chris Wright <chrisw@...s-sol.org>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
	rostedt@...dmis.org, chrisw@...s-sol.org, tglx@...utronix.de
Subject: [tip:tracing/core] x86: use native register access for native tlb flushing

Commit-ID:  d7285c6b5c54397fdf112c2fb98ee43193173aa9
Gitweb:     http://git.kernel.org/tip/d7285c6b5c54397fdf112c2fb98ee43193173aa9
Author:     Chris Wright <chrisw@...s-sol.org>
AuthorDate: Thu, 23 Apr 2009 10:21:38 -0700
Committer:  Steven Rostedt <rostedt@...dmis.org>
CommitDate: Thu, 23 Apr 2009 23:05:03 -0400

x86: use native register access for native tlb flushing

currently these are paravirtulaized, doesn't appear any callers rely on
this (no pv_ops backends are using native_tlb and overriding cr3/4
access).

[ Impact: fix lockdep warning with paravirt and function tracer ]

Signed-off-by: Chris Wright <chrisw@...s-sol.org>
LKML-Reference: <20090423172138.GR3036@...uoia.sous-sol.org>
Signed-off-by: Steven Rostedt <rostedt@...dmis.org>


---
 arch/x86/include/asm/tlbflush.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index d3539f9..e2927c5 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -17,7 +17,7 @@
 
 static inline void __native_flush_tlb(void)
 {
-	write_cr3(read_cr3());
+	native_write_cr3(native_read_cr3());
 }
 
 static inline void __native_flush_tlb_global(void)
@@ -32,11 +32,11 @@ static inline void __native_flush_tlb_global(void)
 	 */
 	raw_local_irq_save(flags);
 
-	cr4 = read_cr4();
+	cr4 = native_read_cr4();
 	/* clear PGE */
-	write_cr4(cr4 & ~X86_CR4_PGE);
+	native_write_cr4(cr4 & ~X86_CR4_PGE);
 	/* write old PGE again and flush TLBs */
-	write_cr4(cr4);
+	native_write_cr4(cr4);
 
 	raw_local_irq_restore(flags);
 }
--
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