linux-kernel - Re: [PATCH 5/8] powerpc: use new macro for .data.cacheline

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Date:	Mon, 18 May 2009 14:23:38 +1000
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	Tim Abbott <tabbott@....EDU>
Cc:	Sam Ravnborg <sam@...nborg.org>,
	Linux kernel mailing list <linux-kernel@...r.kernel.org>,
	Anders Kaseorg <andersk@....EDU>,
	Waseem Daher <wdaher@....EDU>,
	Denys Vlasenko <vda.linux@...glemail.com>,
	Jeff Arnold <jbarnold@....EDU>,
	Paul Mackerras <paulus@...ba.org>, linuxppc-dev@...abs.org
Subject: Re: [PATCH 5/8] powerpc: use new macro for .data.cacheline_aligned
 section.

On Thu, 2009-04-30 at 19:56 -0400, Tim Abbott wrote:
> .data.cacheline_aligned should not need a separate output section;
> this change moves it into the .data section.
> 
> Since there isn't an ALIGN() directive before the
> .data.cacheline_aligned scetion in the current linker script, I'd like
> an ack from one of the powerpc maintainers that L1_CACHE_BYTES is the
> correct alignment here.

Yes, that's the right size.

Also. that looks like a bug to me in the current stuff. I'm queuing your
patch set for .31 but I'll stick a "fix" in .30 for that just in case
which unfortunately means your patches will probably need to be rebased.

Cheers,
Ben.

> Signed-off-by: Tim Abbott <tabbott@....edu>
> Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
> Cc: Paul Mackerras <paulus@...ba.org>
> Cc: linuxppc-dev@...abs.org
> ---
>  arch/powerpc/kernel/vmlinux.lds.S |    5 +----
>  1 files changed, 1 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
> index 4223892..e769717 100644
> --- a/arch/powerpc/kernel/vmlinux.lds.S
> +++ b/arch/powerpc/kernel/vmlinux.lds.S
> @@ -223,6 +223,7 @@ SECTIONS
>  	.data : AT(ADDR(.data) - LOAD_OFFSET) {
>  		PAGE_ALIGNED_DATA
>  		NOSAVE_DATA
> +		CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
>  		DATA_DATA
>  #ifdef CONFIG_PPC32
>  		*(.sdata)
> @@ -260,10 +261,6 @@ SECTIONS
>  		*(.data.init_task)
>  	}
>  
> -	.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
> -		*(.data.cacheline_aligned)
> -	}
> -
>  	. = ALIGN(L1_CACHE_BYTES);
>  	.data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) {
>  		*(.data.read_mostly)

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