| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 22 May 2009 22:05:36 +0200 From: Samuel Thibault <samuel.thibault@...-lyon.org> To: "Michael S. Zick" <lkml@...ethan.org> Cc: Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org Subject: Re: [BUG FIX] Make x86_32 uni-processor Atomic ops, Atomic Michael S. Zick, le Fri 22 May 2009 14:53:39 -0500, a écrit : > Ref: http://developer.intel.com/Assets/PDF/manual/253666.pdf > Manual page: 3-590 PDF page: 638 > Summary: Processors prior to P-4 can take an interrupt between > the read cycle and the write cycle. Which is why opcode 0xF0 exists. Where do you see page 638/639 talking about interrupts? It talks about multi-processor machines. Samuel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists