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Date:	Thu, 25 Jun 2009 10:47:33 +0200
From:	Yegor Yefremov <yegorslists@...glemail.com>
To:	David Woodhouse <dwmw2@...radead.org>
Cc:	linux-kernel@...r.kernel.org
Subject: Re: Add support for the SST 39VF3202, 39VF6401B and 39VF6402B flash 
	chips

>> Add support for the SST 39VF3202, 39VF6401B and 39VF6402B flash chips
>>
>> - extend struct amd_flash_info to enable 8 erase regions for 8Mb flash chips
>
> If you didn't mean 8,000,000 bits, don't say it. Did you mean 8MiB?

Sure I mean 8MiB

>> - change erase block command to 0x50 due to the differences between
>> 39VF6401/02 and 39VF6401B/02B chips
>
> Hm, can you elucidate?

Please refer to the data sheets Table 6:
39VF6401B data sheet http://www.sst.com/downloads/datasheet/S71288.pdf
39VF6401 data sheet http://www.sst.com/downloads/datasheet/S71223-03.pdf

The difference in the 6th bus write cycle. 39VF6401B uses 0x50 and
39VF6401 uses 0x30.

> And should that be done as a quirk instead?

How should I do it? The commend is not a part of any structure. Can we
add such a field to the  struct amd_flash_info describing erase
sequence?

Yegor
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