linux-kernel - Re: [tip:perfcounters/urgent] x86: atomic64: The atomic64_t data type should be 8 bytes aligned on 32-bit too

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Date:	Fri, 3 Jul 2009 09:58:58 -0700 (PDT)
From:	Linus Torvalds <torvalds@...ux-foundation.org>
To:	mingo@...hat.com, "H. Peter Anvin" <hpa@...or.com>,
	paulus@...ba.org, acme@...hat.com,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	eric.dumazet@...il.com, a.p.zijlstra@...llo.nl, efault@....de,
	arnd@...db.de, fweisbec@...il.com, dhowells@...hat.com,
	Andrew Morton <akpm@...ux-foundation.org>, tglx@...utronix.de,
	Ingo Molnar <mingo@...e.hu>
Subject: Re: [tip:perfcounters/urgent] x86: atomic64: The atomic64_t data
 type should be 8 bytes aligned on 32-bit too

On Fri, 3 Jul 2009, tip-bot for Eric Dumazet wrote:
> 
> x86: atomic64: The atomic64_t data type should be 8 bytes aligned on 32-bit too
> 
> Locked instructions on two cache lines at once are painful. If
> atomic64_t uses two cache lines, my test program is 10x slower.
> 
> The chance for that is significant: 4/32 or 12.5%.

Btw, the comments here are not strictly correct.

It's not necessarily even about "two cachelines". It's true that crossing 
cachelines is extra painful, but from a CPU core angle, there's another 
access width that matters almost as much, namely the width of the bus 
between the core and the L1 cache. If it's not aligned to that, the core 
needs to do each 8-byte read/write as two accesses, even if it's to the 
same cacheline, and that complicates things.

The cacheline itself is generally larger than the cache access width. I 
could easily see a 64B cacheline, but a 256b (32B) bus between the cache 
and the core.

Making the atomics be naturally aligned means that you never cross either 
one, of course.

			Linus
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