linux-kernel - Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned

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Date:	Fri, 04 Sep 2009 09:04:28 -0700
From:	Jeremy Fitzhardinge <jeremy@...p.org>
To:	Tejun Heo <tj@...nel.org>
CC:	"H. Peter Anvin" <hpa@...or.com>, mingo@...hat.com,
	linux-kernel@...r.kernel.org, jeremy.fitzhardinge@...rix.com,
	stable@...nel.org, tglx@...utronix.de, mingo@...e.hu,
	linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base
 is cache aligned

On 09/03/09 22:06, Tejun Heo wrote:
>>> Heh... here's a naive and hopeful plan.  How about we beg gcc
>>> developers to allow different segment register and offset in newer gcc
>>> versions and then use the same one when building with the new gcc?
>>> This should solve the i386 problem too.  It would be the best as we
>>> get to keep the separate segment register from the userland.  Too
>>> hopeful?
>>>       
>> I think it's possible to set the register in more recent gcc.  Doing the
>> sane thing and having a symbol for an offset is probably worse.
>>     
> I was thinking about altering the build process so that we can use sed
> to substitute %gs:40 with %fs:40 while compiling.  If it's already
> possible to override the register in more recent gcc, no need to go
> into that horror.
>   

Ideally we'd like to get rid of the constant offset too.  If we could
change it to %[fg]s:__gcc_stack_canary_offset on both 32-bit and 64-bit,
it would give us a lot more flexibility.  __gcc_stack_canary_offset
could be weakly defined to 20/40 for backwards compatibility, but we
could override it to point to a normal percpu variable.

    J
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