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Date: Mon, 2 Nov 2009 16:17:43 GMT
From: tip-bot for Suresh Siddha <suresh.b.siddha@...el.com>
To: linux-tip-commits@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
ebiederm@...ssion.com, garyhade@...ibm.com,
suresh.b.siddha@...el.com, tglx@...utronix.de, mingo@...e.hu
Subject: [tip:x86/apic] x86: Use EOI register in io-apic on intel platforms
Commit-ID: b3ec0a37a7907813bb4fb85a2d94102c152470b7
Gitweb: http://git.kernel.org/tip/b3ec0a37a7907813bb4fb85a2d94102c152470b7
Author: Suresh Siddha <suresh.b.siddha@...el.com>
AuthorDate: Mon, 26 Oct 2009 14:24:35 -0800
Committer: Ingo Molnar <mingo@...e.hu>
CommitDate: Mon, 2 Nov 2009 15:56:36 +0100
x86: Use EOI register in io-apic on intel platforms
IO-APIC's in intel chipsets support EOI register starting from
IO-APIC version 2. Use that when ever we need to clear the
IO-APIC RTE's RemoteIRR bit explicitly.
Signed-off-by: Suresh Siddha <suresh.b.siddha@...el.com>
Acked-by: Gary Hade <garyhade@...ibm.com>
Cc: Eric W. Biederman <ebiederm@...ssion.com>
LKML-Reference: <20091026230001.947855317@...-t61.sc.intel.com>
[ Marked use_eio_reg as __read_mostly, fixed small details ]
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
arch/x86/kernel/apic/io_apic.c | 81 ++++++++++++++++++++++++++-------------
1 files changed, 54 insertions(+), 27 deletions(-)
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 4e886ef..31e9db3 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2492,6 +2492,51 @@ static void ack_apic_edge(unsigned int irq)
atomic_t irq_mis_count;
+static int use_eoi_reg __read_mostly;
+
+static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
+{
+ struct irq_pin_list *entry;
+
+ for_each_irq_pin(entry, cfg->irq_2_pin) {
+ if (irq_remapped(irq))
+ io_apic_eoi(entry->apic, entry->pin);
+ else
+ io_apic_eoi(entry->apic, cfg->vector);
+ }
+}
+
+static void eoi_ioapic_irq(struct irq_desc *desc)
+{
+ struct irq_cfg *cfg;
+ unsigned long flags;
+ unsigned int irq;
+
+ irq = desc->irq;
+ cfg = desc->chip_data;
+
+ spin_lock_irqsave(&ioapic_lock, flags);
+ __eoi_ioapic_irq(irq, cfg);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
+}
+
+static int ioapic_supports_eoi(void)
+{
+ struct pci_dev *root;
+
+ root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+ if (root && root->vendor == PCI_VENDOR_ID_INTEL &&
+ mp_ioapics[0].apicver >= 0x2) {
+ use_eoi_reg = 1;
+ printk(KERN_INFO "IO-APIC supports EOI register\n");
+ } else
+ printk(KERN_INFO "IO-APIC doesn't support EOI\n");
+
+ return 0;
+}
+
+fs_initcall(ioapic_supports_eoi);
+
static void ack_apic_level(unsigned int irq)
{
struct irq_desc *desc = irq_to_desc(irq);
@@ -2575,37 +2620,19 @@ static void ack_apic_level(unsigned int irq)
/* Tail end of version 0x11 I/O APIC bug workaround */
if (!(v & (1 << (i & 0x1f)))) {
atomic_inc(&irq_mis_count);
- spin_lock(&ioapic_lock);
- __mask_and_edge_IO_APIC_irq(cfg);
- __unmask_and_level_IO_APIC_irq(cfg);
- spin_unlock(&ioapic_lock);
+
+ if (use_eoi_reg)
+ eoi_ioapic_irq(desc);
+ else {
+ spin_lock(&ioapic_lock);
+ __mask_and_edge_IO_APIC_irq(cfg);
+ __unmask_and_level_IO_APIC_irq(cfg);
+ spin_unlock(&ioapic_lock);
+ }
}
}
#ifdef CONFIG_INTR_REMAP
-static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
-{
- struct irq_pin_list *entry;
-
- for_each_irq_pin(entry, cfg->irq_2_pin)
- io_apic_eoi(entry->apic, entry->pin);
-}
-
-static void
-eoi_ioapic_irq(struct irq_desc *desc)
-{
- struct irq_cfg *cfg;
- unsigned long flags;
- unsigned int irq;
-
- irq = desc->irq;
- cfg = desc->chip_data;
-
- spin_lock_irqsave(&ioapic_lock, flags);
- __eoi_ioapic_irq(irq, cfg);
- spin_unlock_irqrestore(&ioapic_lock, flags);
-}
-
static void ir_ack_apic_edge(unsigned int irq)
{
ack_APIC_irq();
--
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