linux-kernel - Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support

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Date:	Fri, 06 Nov 2009 16:34:41 +0800
From:	Wu Zhangjin <wuzhangjin@...il.com>
To:	Ralf Baechle <ralf@...ux-mips.org>
Cc:	linux-mips@...ux-mips.org, LKML <linux-kernel@...r.kernel.org>,
	huhb@...ote.com, yanh@...ote.com, Zhang Le <r0bertz@...too.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Nicholas Mc Guire <der.herr@...r.at>, zhangfx@...ote.com,
	liujl@...ote.com
Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support

Hi,

On Thu, 2009-11-05 at 14:16 +0100, Ralf Baechle wrote:
[...]
> > +static int mach_i8259_irq(void)
> > +{
> > +	int irq, isr, imr;
> > +
> > +	irq = -1;
> > +
> > +	if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
> > +		imr = inb(0x21) | (inb(0xa1) << 8);
> > +		isr = inb(0x20) | (inb(0xa0) << 8);
> > +		isr &= ~0x4;	/* irq2 for cascade */
> > +		isr &= ~imr;
> > +		irq = ffs(isr) - 1;
> > +	}
> 
> Any reason why you're not using i8259_irq() from <asm/i8259.h> here?
> That function not only gets the locking right, it also minimizes the number
> of accesses to the i8259 - which even on modern silicon can be stuningly
> slow.

Just checked it again, seems we can only access the ISR registers, but
even if with this restriction, we can also optimize it to minimize the
number of accesses to the i8259, this is the new version:

+ isr = inb(PIC_MASTER_CMD) &
+     ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
+ if (!isr)
+    isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;

Will resend it with this version.

Thanks,
	Wu Zhangjin

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