lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 02 Dec 2009 23:34:40 -0500
From:	Michael Breuer <mbreuer@...jas.com>
To:	Arjan van de Ven <arjan@...radead.org>
Cc:	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: Bug (minor): microcode_intel.c applies updates to hyperthreaded
 cores

Fair point - guess it's a different bug. Looks like the mechanism sets 
up the requests first for all cpus, then loads them. apply_microcode 
doesn't recheck.

CPU is a core i7 920; ht enabled. cpuinfo shows 4 cores; 8 cpus, as 
expected.




 From my log:
Dec  2 16:53:47 mail kernel: microcode: CPU0 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU1 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU2 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU3 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU4 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU5 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU6 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU7 sig=0x106a5, pf=0x2, 
revision=0xf
Dec  2 16:53:47 mail kernel: platform microcode: firmware: requesting 
intel-ucode/06-1a-05
Dec  2 16:53:47 mail kernel: microcode: CPU0 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU1 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU2 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU3 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU4 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU5 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU6 updated to revision 0x11, 
date = 2009-04-14
Dec  2 16:53:47 mail kernel: microcode: CPU7 updated to revision 0x11, 
date = 2009-04-14


On 12/02/2009 11:20 PM, Arjan van de Ven wrote:
> On Wed, 02 Dec 2009 23:06:19 -0500
> Michael Breuer<mbreuer@...jas.com>  wrote:
>
>    
>> According to spec, microcode should only be applied to actual cores.
>> As things are currently structured, looks like the fix would be in
>> microcode_core.c. I don't think changing the loop to look for cores
>> vs. cpu's would affect anything adversely, but honestly am not
>> familiar enough with this code or other cpu types to be sure.
>>
>>      
> isn't this
>
> for each (logical) cpu
>     check microcode version of the cpu
>     if too old, apply microcode
>
> the 2nd pair of a hyperthreading pair will never see the 'too old' case
> happen...
>
>
>    

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists