linux-kernel - Re: [PATCH 09/14] pci: introduce pci_assign_unassigned_bridge

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 13 Jan 2010 16:31:45 +0900
From:	Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>
To:	Yinghai Lu <yinghai@...nel.org>
CC:	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Ingo Molnar <mingo@...e.hu>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Ivan Kokshaysky <ink@...assic.park.msu.ru>,
	Alex Chiang <achiang@...com>,
	Bjorn Helgaas <bjorn.helgaas@...com>,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org
Subject: Re: [PATCH 09/14] pci: introduce pci_assign_unassigned_bridge_resources

Yinghai Lu wrote:
> On 01/12/2010 04:50 PM, Kenji Kaneshige wrote:
>> Yinghai Lu wrote:
>>> for pciehp to use it later
>>>
>>> pci_setup_bridge() will not check enabled for the slot bridge, otherwise
>>> update res is not updated to bridge BAR. that is bridge is enabled already for
>>> port service.
>>>
>>> -v2: update it with resource_list_x
>>>
>>> Signed-off-by: Yinghai Lu <yinghai@...nel.org>
> ...
> 
>>> +
>>> +void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
>>> +{
>>> +	struct pci_bus *bus;
>>> +	struct pci_bus *parent = bridge->subordinate;
>>> +	int retval;
>>> +
>>> +	pci_bus_size_bridges(parent);
>>> +	pci_clear_master(bridge);
>> I have a concern about clearing bus master enable bit here, though
>> I'm not sure about it. I'm wondering if clearing bus master enable
>> bit might have some bad effect for the port services to work. For
>> example, does MSI interrupt work without enabling bus mastering?
> but we set that pci_set_master right away after we assign the new resource

Yes, I know you set bus master enable bit again.

In my understanding, bus master enable bit of the bridge is
cleared temporary while its port service driver is working.
I'm worrying about this temporary operation. For example,
I'm worrying about whether the MSI interrupt works, if some
port service generates interrupts when bus master enable bit
is cleared temporary.

Thanks,
Kenji Kaneshige


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/