linux-kernel - Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs

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Date:	Mon, 18 Jan 2010 15:21:38 +0800
From:	Huaxu Wan <huaxu.wan@...ux.intel.com>
To:	Jean Delvare <khali@...ux-fr.org>
Cc:	Robert Hancock <hancockrwd@...il.com>, huaxu.wan@...el.com,
	Yuhong Bao <yuhongbao_386@...mail.com>,
	lm-sensors@...sensors.org, linux-kernel@...r.kernel.org,
	yong.y.wang@...ux.intel.com
Subject: Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom
 N450/D410/D510 CPUs

On 21:05 Sun 17 Jan, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> > 
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the 
> > problems this creates for their ION chipset). I'm assuming this patch is 
> > checking for the host bridge device though, that is integrated into the 
> > CPU and would always be present.
> 
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
> 
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.

Actually, all the Atom processors share the same CPUID(0x1C) and the
worse is not all of them has the same TjMax. That's a big problem. 

Thanks
Huaxu
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