linux-kernel - Re: [PATCH 3/5] gic: Add set

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Date:	Wed, 27 Jan 2010 23:09:58 +0000
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	adharmap@...eaurora.org
Cc:	linux-arm-kernel@...ts.infradead.org, Ingo Molnar <mingo@...e.hu>,
	Catalin Marinas <catalin.marinas@....com>,
	Yinghai Lu <yinghai@...nel.org>,
	Tony Lindgren <tony@...mide.com>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	Kevin Hilman <khilman@...prootsystems.com>,
	Kalle Valo <kalle.valo@....fi>, Jean Pihet <jpihet@...sta.com>,
	Linus Walleij <linus.walleij@...ricsson.com>,
	Colin Tuckley <colin.tuckley@....com>,
	Philby John <pjohn@...mvista.com>,
	Srinidhi Kasagar <srinidhi.kasagar@...ricsson.com>,
	Alessandro Rubini <rubini@...pv.it>,
	Andrea Gallo <andrea.gallo@...ricsson.com>,
	linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org,
	Abhijeet Dharmapurikar <adharmap@...cinc.com>
Subject: Re: [PATCH 3/5] gic: Add set_type callback

On Wed, Jan 27, 2010 at 11:32:27AM -0800, adharmap@...eaurora.org wrote:
> +	if (irq > 1020)
> +		return -1;

*unprintable*.  Always use proper error codes.

> +
> +	/*
> +	* Two bits each, calc the register and bit, 16 per 32 bit register
> +	* accessible long word only
> +	* But the field is NxN 1xN and rising/falling
> +	*/
> +	register_index = (irq/16)<<2;
> +	bit_index = (irq & 0xF)<<1;
> +
> +	spin_lock(&irq_controller_lock);
> +	reg_value = readl(gic_dist_base(irq) + GIC_DIST_CONFIG +
> +						register_index);
> +	/*
> +	* keep the nxn and 1xn , mask the edge level
> +	* Edge is 1, level 0
> +	*/
> +	reg_value = (reg_value & ~(2<<bit_index));
> +	if (flow_type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) {
> +		reg_value |= (2<<bit_index);
> +		writel(reg_value, gic_dist_base(irq) + GIC_DIST_CONFIG
> +							+ register_index);
> +		__set_irq_handler_unlocked(irq, handle_edge_irq);
> +	}
> +
> +	if (flow_type & (IRQ_TYPE_LEVEL_HIGH|IRQ_TYPE_LEVEL_LOW)) {
> +		writel(reg_value, gic_dist_base(irq) + GIC_DIST_CONFIG
> +							+ register_index);
> +		__set_irq_handler_unlocked(irq, handle_level_irq);
> +	}

This needs to exclude the first 32 interrupts, where the interrupt
configuration is either read-only or banked between multiprocessor
CPUs.
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