linux-kernel - Re: [PATCH] perf_events: AMD event scheduling (v3)

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Date:	Wed, 10 Feb 2010 14:04:54 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	linux-kernel@...r.kernel.org, mingo@...e.hu, paulus@...ba.org,
	davem@...emloft.net, fweisbec@...il.com, robert.richter@....com,
	perfmon2-devel@...ts.sf.net, eranian@...il.com
Subject: Re: [PATCH] perf_events: AMD event scheduling (v3)

On Wed, Feb 10, 2010 at 12:59 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Mon, 2010-02-08 at 17:17 +0200, Stephane Eranian wrote:
>>         This patch adds correct AMD Northbridge event scheduling.
>>         It must be applied on top tip-x86 + hw_perf_enable() fix.
>>
>>         NB events are events measuring L3 cache, Hypertransport
>>         traffic. They are identified by an event code  >= 0xe0.
>>         They measure events on the Northbride which is shared
>>         by all cores on a package. NB events are counted on a
>>         shared set of counters. When a NB event is programmed
>>         in a counter, the data actually comes from a shared
>>         counter. Thus, access to those counters needs to be
>>         synchronized.
>>
>>         We implement the synchronization such that no two cores
>>         can be measuring NB events using the same counters. Thus,
>>         we maintain a per-NB * allocation table. The available slot
>>         is propagated using the event_constraint structure.
>>
>>         The 2nd version takes into account the changes on how
>>         constraints are stored by the scheduling code.
>>
>>         The 3rd version fixes formatting issues, code readability
>>         and one bug in amd_put_event_constraints().
>>
>>         Signed-off-by: Stephane Eranian <eranian@...gle.com>
>
> OK, took this with the below merged in.
>
> ---
> Index: linux-2.6/arch/x86/kernel/cpu/perf_event.c
> ===================================================================
> --- linux-2.6.orig/arch/x86/kernel/cpu/perf_event.c
> +++ linux-2.6/arch/x86/kernel/cpu/perf_event.c
> @@ -81,7 +81,7 @@ struct event_constraint {
>  };
>
>  struct amd_nb {
> -       int nb_id;  /* Northbridge id */
> +       int nb_id;  /* NorthBridge id */
>        int refcnt; /* reference count */
>        struct perf_event *owners[X86_PMC_IDX_MAX];
>        struct event_constraint event_constraints[X86_PMC_IDX_MAX];
> @@ -2268,7 +2268,7 @@ static inline int amd_is_nb_event(struct
>        u64 val = hwc->config & K7_EVNTSEL_EVENT_MASK;
>        /* event code : bits [35-32] | [7-0] */
>        val = (val >> 24) | (val & 0xff);
> -       return val >= 0x0e0;
> +       return val >= 0xe00;
>  }
>
I don't understand the change from 0xe0 to 0xe00.
That's not the same thing at all.
Event select is bits 0-7 + 32-35.
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