linux-kernel - Re: USB mass storage and ARM cache coherency

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Date:	Tue, 16 Feb 2010 10:07:20 +0100
From:	Oliver Neukum <oliver@...kum.org>
To:	"Shilimkar, Santosh" <santosh.shilimkar@...com>
Cc:	Catalin Marinas <catalin.marinas@....com>,
	Pavel Machek <pavel@....cz>, Greg KH <greg@...ah.com>,
	"Russell King - ARM Linux" <linux@....linux.org.uk>,
	Matthew Dharm <mdharm-kernel@...-eyed-alien.net>,
	Sergei Shtylyov <sshtylyov@...mvista.com>,
	Ming Lei <tom.leiming@...il.com>,
	Sebastian Siewior <bigeasy@...utronix.de>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	"linux-kernel" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel" <linux-arm-kernel@...ts.infradead.org>,
	"Mankad, Maulik Ojas" <x0082077@...com>
Subject: Re: USB mass storage and ARM cache coherency

Am Dienstag, 16. Februar 2010 09:55:55 schrieb Shilimkar, Santosh:
> > This seems wrong to me. Buffers for control transfers may be transfered
> > by DMA, so the caches must be flushed on architectures whose caches
> > are not coherent with respect to DMA.
> Indeed and that's what I mentioned in the comment. But we shouldn't have dma 
> cache maintenance operations done for the buffers which would use pio based transfer.

Given that the generic layer can't know which buffers will be used for DMA
that would require a callback into the hcd driver.

> > Would you care to elaborate on the exact nature of the bug you are fixing?
> On the OMAP4 (ARM cortex-a9) platform, the enumeration fails because control
> transfer buffers are corrupted. On our platform, we use PIO mode for control 
> transfers and DMA for bulk transfers.
> 
> The current stack performs dma cache maintenance even for the PIO transfers
> which leads to the corruption issue. The control buffers are handled by CPU 
> and they already coherent from CPU point of view.

How does the mapping corrupt buffers? It might impact performance, but why
do you see corruption?

	Regards
		Oliver
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