linux-kernel - Re: [PATCH RT] ehea: make receive irq handler non-threaded (IRQF

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Date:	Thu, 20 May 2010 09:37:47 +0200
From:	Jan-Bernd Themann <THEMANN@...ibm.com>
To:	michael@...erman.id.au
Cc:	Brian King <brking@...ux.vnet.ibm.com>,
	Doug Maxey <doug.maxey@...ibm.com>, dvhltc@...ux.vnet.ibm.com,
	Darren Hart <dvhltc@...ibm.com>, linux-kernel@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org, niv@...ux.vnet.ibm.com,
	Thomas Gleixner <tglx@...utronix.de>,
	Will Schmidt <will_schmidt@...t.ibm.com>
Subject: Re: [PATCH RT] ehea: make receive irq handler non-threaded (IRQF_NODELAY)

Hi,


Michael Ellerman <michael@...erman.id.au> wrote on 20.05.2010 03:34:08:


> Subject:
>
> Re: [PATCH RT] ehea: make receive irq handler non-threaded (IRQF_NODELAY)
>
> On Wed, 2010-05-19 at 23:08 +0200, Thomas Gleixner wrote:
> > On Wed, 19 May 2010, Thomas Gleixner wrote:
> > > > I'm still not clear on why the ultimate solution wasn't to
> have XICS report
> > > > edge triggered as edge triggered. Probably some complexity of
> the entire power
> > > > stack that I am ignorant of.
> > > >
> > > > > Apart from the issue of loosing interrupts there is also thefact
that
> > > > > masking on the XICS requires an RTAS call which takes a global
lock.
> > >
> > > Right, I'd love to avoid that but with real level interrupts we'd run
> > > into an interrupt storm. Though another solution would be to issue
the
> > > EOI after the threaded handler finished, that'd work as well, but
> > > needs testing.
> >
> > Thought more about that. The case at hand (ehea) is nasty:
> >
> > The driver does _NOT_ disable the rx interrupt in the card in the rx
> > interrupt handler - for whatever reason.
>
> Yeah I saw that, but I don't know why it's written that way. Perhaps
> Jan-Bernd or Doug will chime in and enlighten us? :)

>From our perspective there is no need to disable interrupts for the RX side
as
the chip does not fire further interrupts until we tell the chip to do so
for a
particular queue. We have multiple receive queues with an own interrupt
each
so that the interrupts can arrive on multiple CPUs in parallel.
Interrupts are enabled again when we leave the NAPI Poll function for the
corresponding
receive queue.

Michael, does this answer your question?

Regards,
Jan-Bernd

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