linux-kernel - Re: [PATCH] x86/sfi: fix ioapic gsi range

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Date:	Mon, 7 Jun 2010 17:01:15 -0700
From:	jacob pan <jacob.jun.pan@...ux.intel.com>
To:	Jacob Pan <jacob.jun.pan@...ux.intel.com>
Cc:	Alan Cox <alan@...ux.intel.com>,
	Arjan van de Ven <arjan@...ux.intel.com>,
	LKML <linux-kernel@...r.kernel.org>,
	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...e.hu>,
	Feng Tang <feng.tang@...el.com>,
	Len Brown <len.brown@...el.com>,
	"Eric W. Biederman" <ebiederm@...ssion.com>
Subject: Re: [PATCH] x86/sfi: fix ioapic gsi range

Jacob Pan Mon,  7 Jun 2010 16:07:24 -0700
>SFI based platforms should have zero based gsi_base for IOAPICs found in SFI
>tables. The current code sets gsi_base starting from 1 when registering ioapic.
>The result is that Moorestown platform would have wrong mp_gsi_routing for each
>ioapic.
>
>Background:
>In Moorestown/Medfield platforms, there is no legacy IRQs, all gsis and irqs
>are one to one mapped, including those < 16. Specifically, IRQ0 and IRQ1 are
>used for per-cpu timers. So without this patch, IOAPIC pin to IRQ mapping is
>off by one.
>
Clarifiction/correction about IRQ0,1. I refer to IOAPIC IRQ #, which is the
IOAPIC RTE entry #. Not in the sense of kernel IRQ# which can be assigned
differently on Moorestown.
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