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Message-ID: <4C164688.2030107@zytor.com>
Date: Mon, 14 Jun 2010 08:11:04 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: "Maciej W. Rozycki" <macro@...ux-mips.org>
CC: Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, jbarnes@...tuousgeek.org
Subject: Re: [PATCH 2/4] x86: ioremap: fix physical address check
On 06/13/2010 11:38 PM, Maciej W. Rozycki wrote:
> On Mon, 14 Jun 2010, Kenji Kaneshige wrote:
>
>> - Architectural limit of physical address in x86 32-bit mode is 40-bit
>> (depnds on processor version).
>
> According to documentation I happen to have handy this limit is actually
> 52 bits (and space is currently available in the data structures used for
> a possible future extension up to 63 bits).
>
Yes. There are, however, very likely bugs in several classes due to
incorrect bitmasks as well as 32-bit PFNs.
We have made the decision based on data structure limitations (and just
usability) to not support more than 2^36 bytes of RAM on 32 bits, but
those data structures should not affect I/O. I;d like to track down and
fix the bugs instead of papering over the problem...
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
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