linux-kernel - Re: [PATCH] tmio_mmc: Make ack_mmc

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Date:	Sat, 21 Aug 2010 07:55:38 +0900
From:	Magnus Damm <magnus.damm@...il.com>
To:	Arnd Hannemann <arnd@...dnet.de>,
	Andrew Morton <akpm@...ux-foundation.org>
Cc:	Yusuke Goda <yusuke.goda.sx@...esas.com>, ian@...menth.co.uk,
	damm@...nsource.se, sameo@...ux.intel.com,
	Paul Mundt <lethal@...ux-sh.org>, g.liakhovetski@....de,
	linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] tmio_mmc: Make ack_mmc_irqs() write-only

On Sat, Aug 21, 2010 at 12:12 AM, Arnd Hannemann <arnd@...dnet.de> wrote:
> Am 20.07.2010 09:51, schrieb Yusuke Goda:
>> This patch updates ack_mmc_irqs() to acknowledge using write instead
>> of read-modify-write. Without this fix the old read-modify-write
>> implementation may acknowledge interrupt sources by mistake. The
>> driver may if so lock-up waiting forever for an interrupt that will
>> never come. Observed with the TMIO_STAT_RXRDY bit together with
>> CMD53 on AR6002 and BCM4318 SDIO cards in polled mode.
>>
>> Signed-off-by: Yusuke Goda <yusuke.goda.sx@...esas.com>
>
> Tested on AP4EVB (sh7372) with SDHC and MMC cards - no regression.
>
> Tested-by: Arnd Hannemann <arnd@...dnet.de>

Thanks, Arnd!

Andrew, is there anything you need to (re)pick-up this patch?

At the current point this patch has:
Signed-off-by: Yusuke Goda <yusuke.goda.sx@...esas.com>
Acked-by: Magnus Damm <damm@...nsource.se>
Tested-by: Arnd Hannemann <arnd@...dnet.de>

Ian Molton also gave his "Acked-by" in a different email thread,
please see below:
On Tue, Jul 27, 2010 at 5:11 PM, Ian Molton <ian@...menth.co.uk> wrote:
> Right now, the docs in question are on my dead fileserver.
>
> Given that, I'll say two things:
>
> 1) Its safe to assume anywhere that does a RMW does it because my
> original docs said so. I dont recall having ever "just done it because
> I had to" when I wrote this.
> 2) The code as is is clearly broken.
>
> I'm not really sure what to do about this. It got made 'doubly broken'
> when we added asic3 support because it was the first platform added
> where you couldnt just do a 32 bit RMW on the pair of registers.
>
> I'm inclined to say "Go Go Go" and see if anything breaks on this one.
> I cant see why the docs want it to be RMW as theres nothing stopping
> the hardware asserting an IRQ even if the CPU disables IRQs / did the
> RMW as an atomic op.
>
> This one therefore,
>
> Acked-by: Ian Molton <ian@...menth.co.uk>

Thanks for the help everyone and sorry about the confused state of things.

/ magnus
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