linux-kernel - Re: [PATCH -v4 1/2] lib, Make gen

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Date:	Wed, 17 Nov 2010 10:18:01 +0800
From:	Huang Ying <ying.huang@...el.com>
To:	Andrew Morton <akpm@...ux-foundation.org>
Cc:	Len Brown <lenb@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Andi Kleen <andi@...stfloor.org>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>,
	Mauro Carvalho Chehab <mchehab@...hat.com>,
	Peter Zijlstra <peterz@...radead.org>
Subject: Re: [PATCH -v4 1/2] lib, Make gen_pool memory allocator lockless

On Wed, 2010-11-17 at 05:50 +0800, Andrew Morton wrote:
> On Tue, 16 Nov 2010 08:53:10 +0800
> Huang Ying <ying.huang@...el.com> wrote:
> 
> > This version of the gen_pool memory allocator supports lockless
> > operation.
> > 
> > This makes it safe to use in NMI handlers and other special
> > unblockable contexts that could otherwise deadlock on locks.  This is
> > implemented by using atomic operations and retries on any conflicts.
> > The disadvantage is that there may be livelocks in extreme cases.  For
> > better scalability, one gen_pool allocator can be used for each CPU.
> > 
> > The lockless operation only works if there is enough memory available.
> > If new memory is added to the pool a lock has to be still taken.  So
> > any user relying on locklessness has to ensure that sufficient memory
> > is preallocated.
> > 
> > The basic atomic operation of this allocator is cmpxchg on long.  On
> > architectures that don't support cmpxchg natively a fallback is used.
> > If the fallback uses locks it may not be safe to use it in NMI
> > contexts on these architectures.
> 
> The code assumes that cmpxchg is atomic wrt NMI.  That would be news to
> me - at present an architecture can legitimately implement cmpxchg()
> with, say, spin_lock_irqsave() on a hashed spinlock.  I don't know
> whether any architectures _do_ do anything like that.  If so then
> that's a problem.  If not, it's an additional requirement on future
> architecture ports.

cmpxchg has been used in that way by ftrace and perf for a long time. So
I agree to make it a requirement on future architecture ports.

> > Signed-off-by: Huang Ying <ying.huang@...el.com>
> > Reviewed-by: Andi Kleen <ak@...ux.intel.com>
> > ---
> >  include/linux/bitmap.h   |    1 
> >  include/linux/genalloc.h |   35 +++++--
> >  lib/bitmap.c             |    2 
> >  lib/genalloc.c           |  228 ++++++++++++++++++++++++++++++++++++++---------
> >  4 files changed, 215 insertions(+), 51 deletions(-)
> > 
> > --- a/include/linux/bitmap.h
> > +++ b/include/linux/bitmap.h
> > @@ -142,6 +142,7 @@ extern void bitmap_release_region(unsign
> >  extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
> >  extern void bitmap_copy_le(void *dst, const unsigned long *src, int nbits);
> >  
> > +#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) % BITS_PER_LONG))
> >  #define BITMAP_LAST_WORD_MASK(nbits)					\
> >  (									\
> >  	((nbits) % BITS_PER_LONG) ?					\
> > --- a/include/linux/genalloc.h
> > +++ b/include/linux/genalloc.h
> > @@ -1,19 +1,26 @@
> > +#ifndef GENALLOC_H
> > +#define GENALLOC_H
> >  /*
> > - * Basic general purpose allocator for managing special purpose memory
> > - * not managed by the regular kmalloc/kfree interface.
> > - * Uses for this includes on-device special memory, uncached memory
> > - * etc.
> > + * Basic general purpose allocator for managing special purpose
> > + * memory, for example, memory not managed by the regular
> > + * kmalloc/kfree interface.  Uses for this includes on-device special
> > + * memory, uncached memory etc.
> > + *
> > + * The gen_pool_alloc, gen_pool_free, gen_pool_avail and gen_pool_size
> > + * implementation is lockless, that is, multiple users can
> > + * allocate/free memory in the pool simultaneously without lock.  This
> > + * also makes the gen_pool memory allocator can be used to
> 
> That sentence needs a fixup.

Yes. I will fix it.
  
> > +static inline int set_bits_ll(unsigned long *addr, unsigned long mask_to_set)
> > +{
> > +	unsigned long val, nval;
> > +
> > +	nval = *addr;
> > +	do {
> > +		val = nval;
> > +		if (val & mask_to_set)
> > +			return -EBUSY;
> > +	} while ((nval = cmpxchg(addr, val, val | mask_to_set)) != val);
> > +
> > +	return 0;
> > +}
> > +
> > +static inline int clear_bits_ll(unsigned long *addr,
> > +				unsigned long mask_to_clear)
> > +{
> > +	unsigned long val, nval;
> > +
> > +	nval = *addr;
> > +	do {
> > +		val = nval;
> > +		if ((val & mask_to_clear) != mask_to_clear)
> > +			return -EBUSY;
> > +	} while ((nval = cmpxchg(addr, val, val & ~mask_to_clear)) != val);
> > +
> > +	return 0;
> > +}
> 
> These are waaaay too big to be inlined.  Let the compiler decide.

Yes. Will change it.

Best Regards,
Huang Ying


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