linux-kernel - Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE

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Date:	Mon, 22 Nov 2010 12:08:52 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Robert Schöne <robert.schoene@...dresden.de>
Cc:	Vince Weaver <vweaver1@...s.utk.edu>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Robert Richter <robert.richter@....com>,
	Ingo Molnar <mingo@...e.hu>, x86 <x86@...nel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and
 PERF_COUNT_HW_CACHE_MISSES for AMD

Robert,

Has there been any progress on this issue?

On Tue, Nov 2, 2010 at 12:08 PM, Robert Schöne
<robert.schoene@...dresden.de> wrote:
>
> >
> Yes, we could use event 4E1 (L3 Cache Misses), but we would need
> different event IDs for the different AMD Families. Not all of them have
> an L3-Cache and even some implementations of Family 10h don't have L3
> either.

I think you could introduce several generic event mapping tables, like what is
done for the various Intel processors, i.e., have variations of the
amd_perfmon_event_map[] table. Then, the kernel would auto-detect the
host CPU and pick the correct table. Same thing would have to be done
for the LL generic cache events if some mappings use Northbridge events.

In general, however, I would recommend not using those generic cache
events to begin with. I think you understand why now. When dealing with
PMU events, you should read the documentation first. Micro-architectures
vary greatly even within the same processor family.
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