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Date: Wed, 2 Mar 2011 20:38:55 +0100
From: Borislav Petkov <bp@...64.org>
To: "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...e.hu>,
Thomas Gleixner <tglx@...utronix.de>
Cc: x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [PATCH RESEND] x86, amd-nb: Misc correctness fixes
Make functions used strictly in bool context return bool. Also, fixup
used types and comments, and make a local function static, while at it.
Signed-off-by: Borislav Petkov <borislav.petkov@....com>
---
Against tip/x86/amd_nb.
arch/x86/include/asm/amd_nb.h | 12 ++++++------
arch/x86/kernel/amd_nb.c | 18 ++++++++++--------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 2b33c4d..527fb96 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -13,7 +13,7 @@ extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
struct bootnode;
-extern int early_is_amd_nb(u32 value);
+extern bool early_is_amd_nb(u32 value);
extern int amd_cache_northbridges(void);
extern void amd_flush_garts(void);
extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn);
@@ -38,18 +38,18 @@ struct amd_northbridge_info {
};
extern struct amd_northbridge_info amd_northbridges;
-#define AMD_NB_GART 0x1
-#define AMD_NB_L3_INDEX_DISABLE 0x2
-#define AMD_NB_L3_PARTITIONING 0x4
+#define AMD_NB_GART BIT(0)
+#define AMD_NB_L3_INDEX_DISABLE BIT(1)
+#define AMD_NB_L3_PARTITIONING BIT(2)
#ifdef CONFIG_AMD_NB
-static inline int amd_nb_num(void)
+static inline u16 amd_nb_num(void)
{
return amd_northbridges.num;
}
-static inline int amd_nb_has_feature(int feature)
+static inline bool amd_nb_has_feature(unsigned feature)
{
return ((amd_northbridges.flags & feature) == feature);
}
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index ed3c2e5..b57ade1 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -48,7 +48,7 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev,
int amd_cache_northbridges(void)
{
- int i = 0;
+ u16 i = 0;
struct amd_northbridge *nb;
struct pci_dev *misc, *link;
@@ -103,9 +103,11 @@ int amd_cache_northbridges(void)
}
EXPORT_SYMBOL_GPL(amd_cache_northbridges);
-/* Ignores subdevice/subvendor but as far as I can figure out
- they're useless anyways */
-int __init early_is_amd_nb(u32 device)
+/*
+ * Ignores subdevice/subvendor but as far as I can figure out
+ * they're useless anyways
+ */
+bool __init early_is_amd_nb(u32 device)
{
const struct pci_device_id *id;
u32 vendor = device & 0xffff;
@@ -113,8 +115,8 @@ int __init early_is_amd_nb(u32 device)
device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device)
- return 1;
- return 0;
+ return true;
+ return false;
}
int amd_get_subcaches(int cpu)
@@ -176,9 +178,9 @@ int amd_set_subcaches(int cpu, int mask)
return 0;
}
-int amd_cache_gart(void)
+static int amd_cache_gart(void)
{
- int i;
+ u16 i;
if (!amd_nb_has_feature(AMD_NB_GART))
return 0;
--
1.7.4.rc2
--
Regards/Gruss,
Boris.
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
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