linux-kernel - Re: [RFC PATCH] x86: stop machine text poke should issue sync core

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Date:	Thu, 03 Mar 2011 14:27:54 +0900
From:	Masami Hiramatsu <masami.hiramatsu.pt@...achi.com>
To:	Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	Arjan van de Ven <arjan@...radead.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Steven Rostedt <rostedt@...dmis.org>,
	Ingo Molnar <mingo@...e.hu>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Andi Kleen <andi@...stfloor.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	linux-kernel@...r.kernel.org,
	"2nddept-manager@....hitachi.co.jp" 
	<2nddept-manager@....hitachi.co.jp>
Subject: Re: [RFC PATCH] x86: stop machine text poke should issue sync core

(2011/03/01 0:24), Mathieu Desnoyers wrote:
> Intel Archiecture Software Developer's Manual section 7.1.3 specifies that a
> core serializing instruction such as "cpuid" should be executed on _each_ core
> before the new instruction is made visible.
> 
> Failure to do so can lead to unspecified behavior (Intel XMC erratas include
> General Protection Fault in the list), so we should avoid this at all cost.
> 
> This problem can affect modified code executed by interrupt handlers after
> interrupt are re-enabled at the end of stop_machine, because no core serializing
> instruction is executed between the code modification and the moment interrupts
> are reenabled.
> 
> Because stop_machine_text_poke performs the text modification from the first CPU
> decrementing stop_machine_first, modified code executed in thread context is
> also affected by this problem. To explain why, we have to split the CPUs in two
> categories: the CPU that initiates the text modification (calls text_poke_smp)
> and all the others. The scheduler, executed on all other CPUs after
> stop_machine, issues an "iret" core serializing instruction, and therefore
> handles core serialization for all these CPUs. However, the text modification
> initiator can continue its execution on the same thread and access the modified
> text without any scheduler call. Given that the CPU that initiates the code
> modification is not guaranteed to be the one actually performing the code
> modification, it falls into the XMC errata.

Thanks Mathieu!
It seems reasonable change. At least I'm OK :)

Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@...achi.com>

> 
> Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
> CC: Peter Zijlstra <peterz@...radead.org>
> CC: Arjan van de Ven <arjan@...radead.org>
> CC: "H. Peter Anvin" <hpa@...or.com>
> CC: Thomas Gleixner <tglx@...utronix.de>
> CC: Steven Rostedt <rostedt@...dmis.org>
> CC: Ingo Molnar <mingo@...e.hu>
> CC: Andrew Morton <akpm@...ux-foundation.org>
> CC: Andi Kleen <andi@...stfloor.org>
> CC: Frederic Weisbecker <fweisbec@...il.com>
> CC: Masami Hiramatsu <masami.hiramatsu.pt@...achi.com>
> ---
>  arch/x86/kernel/alternative.c |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> Index: linux-2.6-lttng/arch/x86/kernel/alternative.c
> ===================================================================
> --- linux-2.6-lttng.orig/arch/x86/kernel/alternative.c
> +++ linux-2.6-lttng/arch/x86/kernel/alternative.c
> @@ -612,6 +612,12 @@ static int __kprobes stop_machine_text_p
>  
>  	flush_icache_range((unsigned long)tpp->addr,
>  			   (unsigned long)tpp->addr + tpp->len);
> +	/*
> +	 * Intel Archiecture Software Developer's Manual section 7.1.3 specifies
> +	 * that a core serializing instruction such as "cpuid" should be
> +	 * executed on _each_ core before the new instruction is made visible.
> +	 */
> +	sync_core();
>  	return 0;
>  }
>  


-- 
Masami HIRAMATSU
2nd Dept. Linux Technology Center
Hitachi, Ltd., Systems Development Laboratory
E-mail: masami.hiramatsu.pt@...achi.com
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