linux-kernel - Re: [PATCH] arch/tile: optimize icache flush

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Date:	Thu, 10 Mar 2011 18:19:54 -0500
From:	Rik van Riel <riel@...hat.com>
To:	Chris Metcalf <cmetcalf@...era.com>
CC:	linux-kernel@...r.kernel.org, a.p.zijlstra@...llo.nl,
	torvalds@...ux-foundation.org, aarcange@...hat.com,
	tglx@...utronix.de, mingo@...e.hu, akpm@...ux-foundation.org,
	"David Miller <davem@...emloft.net>" <linux-arch@...r.kernel.org>,
	linux-mm@...ck.org, benh@...nel.crashing.org,
	hugh.dickins@...cali.co.uk, mel@....ul.ie, npiggin@...nel.dk,
	rmk@....linux.org.uk, schwidefsky@...ibm.com
Subject: Re: [PATCH] arch/tile: optimize icache flush

On 03/10/2011 01:05 PM, Chris Metcalf wrote:
> Tile has incoherent icaches, so they must be explicitly invalidated
> when necessary.  Until now we have done so at tlb flush and context
> switch time, which means more invalidation than strictly necessary.
> The new model for icache flush is:
>
> - When we fault in a page as executable, we set an "Exec" bit in the
>    "struct page" information; the bit stays set until page free time.
>    (We use the arch_1 page bit for our "Exec" bit.)
>
> - At page free time, if the Exec bit is set, we do an icache flush.
>    This should happen relatively rarely: e.g., deleting a binary from disk,
>    or evicting a binary's pages from the page cache due to memory pressure.
>
> Signed-off-by: Chris Metcalf<cmetcalf@...era.com>

Nice trick.

Acked-by: Rik van Riel <riel@...hat.com>

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