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Date:	Mon, 25 Apr 2011 19:41:10 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Andi Kleen <ak@...ux.intel.com>
Cc:	Peter Zijlstra <peterz@...radead.org>, arun@...rma-home.net,
	Stephane Eranian <eranian@...gle.com>,
	Arnaldo Carvalho de Melo <acme@...radead.org>,
	linux-kernel@...r.kernel.org, Lin Ming <ming.m.lin@...el.com>,
	Arnaldo Carvalho de Melo <acme@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>, eranian@...il.com,
	Arun Sharma <asharma@...com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [generalized cache events] Re: [PATCH 1/1] perf tools: Add
 missing user space support for config1/config2


* Andi Kleen <ak@...ux.intel.com> wrote:

> > You're so skilled at not actually saying anything useful. Are you
> > perchance referring to the fact that the IP reported in the PEBS data is
> > exactly _one_ instruction off? Something that is demonstrated to be
> > fixable?
> 
> It's one instruction off the instruction that was retired when the PEBS 
> interrupt was ready, but not one instruction off the instruction that caused 
> the event. There's still skid in triggering the interrupt.

Peter answered this in the other mail:

 |
 | Sure, but who cares? So your period isn't exactly what you specified, but 
 | the effective period will have an average and a fairly small stdev (assuming 
 | the initial period is much larger than the relatively few cycles it takes to 
 | arm the PEBS assist), therefore you still get a fairly uniform spread.
 |

... and the resulting low level of noise in the average period length is what 
matters. The instruction itself will still be one of the hotspot instructions, 
statistically.

Thanks,

	Ingo
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