linux-kernel - Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2

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Date:	Tue, 26 Apr 2011 09:38:47 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Vince Weaver <vweaver1@...s.utk.edu>
Cc:	Arnaldo Carvalho de Melo <acme@...radead.org>,
	linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Stephane Eranian <eranian@...il.com>,
	Lin Ming <ming.m.lin@...el.com>,
	Arnaldo Carvalho de Melo <acme@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Subject: Re: [PATCH 1/1] perf tools: Add missing user space support for
 config1/config2


* Vince Weaver <vweaver1@...s.utk.edu> wrote:

> On Mon, 25 Apr 2011, Ingo Molnar wrote:
> 
> > 
> > * Vince Weaver <vweaver1@...s.utk.edu> wrote:
> > 
> > > [...] The kernel has no business telling users which perf events are 
> > > interesting, or limiting them! [...]
> > 
> > The policy is very simple and common-sense: if a given piece of PMU 
> > functionality is useful enough to be exposed via a raw interface, then
> > it must be useful enough to be generalized as well.
> 
> what does that even mean?  How do you "generalize" a functionality like 
> writing a value to an auxiliary MSR register?

Here are a few examples:

 - the pure act of task switching sometimes involves writing to MSRs. How is it
   generalized? The concept of 'processes/threads' is offered to user-space and
   thus this functionality is generalized - the raw MSRs are not just passed
   through to user-space.

 - a wide range of VMX (virtualization) functionality on Intel CPUs operates via 
   writing special values to specific MSR registers. How is it 'generalized'? A 
   meaningful, structured ABI is provided to user-space in form of the KVM 
   device and associated semantics. The raw MSRs are not just passed through to
   user-space.

 - the ability of CPUs to change frequency is offered via writing special
   values to special MSRs. How is this generalized? The cpufreq subsystem 
   offers a frequency/cpu API and associated abstractions - the raw MSRs are 
   not just passed through to user-space.

 - in the context of perf events we generalize the concept of an 'event' and
   we abstract out common, CPU model neutral CPU hardware concepts like 
   'cycles', 'instructions', 'branches' and a simplified cache hierarchy - and 
   offer those events as generic events to user-space. We do not just pass the 
   raw MSRs through to user-space.

 - [ etc. - a lot of useful CPU functionality is MSR driven, the PMU is nothing
     special there. ]

The kernel development process is in essence an abstraction engine, and if you 
expect something else you'll probably be facing a lot of frustrating episodes 
in the future as well where others try to abstract out meaningful 
generalizations.

Thanks,

	Ingo
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