linux-kernel - Re: Bug in MTD NAND ONFI chipsize detection

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Date:	Thu, 12 May 2011 17:39:55 +0200
From:	Matthieu CASTET <matthieu.castet@...rot.com>
To:	Nitin Garg <nitingarg98@...il.com>
CC:	Andrew Morton <akpm@...ux-foundation.org>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	David Woodhouse <dwmw2@...radead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: Bug in MTD NAND ONFI chipsize detection

Nitin Garg a écrit :
> I do not see any diff for mtd.
> 
ONFI spec say [1].

Why this doesn't apply to mtd ?


[1]
    3.1.2. Logical Unit Selection
Logical units within one target share a single data bus with the host. The host
shall ensure that
only one LUN is selected for data output to the host at any particular point in
time to avoid bus
contention.
The host selects a LUN for future data output by issuing a Read Status Enhanced
command to
that LUN. The Read Status Enhanced command shall deselect the output path for
all LUNs that
are not addressed by the command. The page register selected for output within
the LUN is
determined by the previous Read (Cache) commands issued, and is not impacted by Read
Status Enhanced.



> Regards,
> Nitin
> 
> On Thu, May 12, 2011 at 2:47 AM, Matthieu CASTET
> <matthieu.castet@...rot.com> wrote:
>> Hi,
>>
>>
>> What's the difference between one lun and multiple lun for mtd ?
>>
>> Aren't any command to select the current lun ?
>>
>> Matthieu
>>
>>
>> Nitin Garg a écrit :
>>> Why isn't my patch going through? re-sending again,
>>>
>>> Signed-off-by: Nitin Garg <nitingarg98@...xxxxx>
>>> ---
>>>  drivers/mtd/nand/nand_base.c |    2 +-
>>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
>>> index c54a4cb..cdf6015 100644
>>> --- a/drivers/mtd/nand/nand_base.c
>>> +++ b/drivers/mtd/nand/nand_base.c
>>> @@ -2892,7 +2892,7 @@ static int nand_flash_detect_onfi(struct
>>> mtd_info *mtd, struct nand_chip *chip,
>>>       mtd->writesize = le32_to_cpu(p->byte_per_page);
>>>       mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
>>>       mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
>>> -     chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
>>> +     chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) *
>>> le32_to_cpu(p->lun_count) * mtd->erasesize;
>>>       busw = 0;
>>>       if (le16_to_cpu(p->features) & 1)
>>>               busw = NAND_BUSWIDTH_16;
> 
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