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Date:	Tue, 28 Jun 2011 18:10:00 +0200
From:	Joerg Roedel <joro@...tes.org>
To:	Joerg Roedel <joerg.roedel@....com>
Cc:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>, Ingo Molnar <mingo@...e.hu>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: Re: [PATCH 0/5] perf support for amd guest/host-only bits v2

On Fri, Jun 17, 2011 at 03:37:29PM +0200, Joerg Roedel wrote:
> this is the second version of the patch-set to support the AMD
> guest-/host only bits in the performance counter MSRs. Due to lack of
> time I havn't looked into emulating support for this feature on Intel or
> other architectures, but the other comments should be worked in. The
> changes to v1 include:
> 
> 	* Rebased patches to v3.0-rc3
> 	* Allow exclude_guest and exclude_host set at the same time
> 	* Reworked event-parse logic for the new exclude-bits
> 	* Only count guest-events per default from perf-kvm

Hi Peter, Ingo,

have you had a chance to look at this patch-set? Are any changes
required?

Regards,
	Joerg

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