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Date: Wed, 31 Aug 2011 21:59:13 -0500 From: Josh Cartwright <joshc@...ux.com> To: Mark Salter <msalter@...hat.com> Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, ming.lei@...onical.com, stern@...land.harvard.edu Subject: Re: [PATCH 1/3] add dma_coherent_write_sync to DMA API On Wed, Aug 31, 2011 at 05:30:12PM -0400, Mark Salter wrote: > On ARMv6/7 DMA-coherent memory is bufferable which means that CPU writes to > coherent memory may still be held in a write buffer for a significant amount > of time. This is largely mitigated by having the MMIO write functions force > a write buffer flush before doing the actual write to the MMIO register. This > forces out previous CPU writes to coherent memory for drivers which write to > a register to inform the device that something was written to memory. However, > this does not mitigate the problem for devices which poll the DMA memory for > changes written by the CPU. One such case was found by ming.lei@...onical.com > in the USB EHCI driver. The EHCI host controller relies at least partly on > polling DMA coherent memory for information from the driver. > > This patch adds a dma_coherent_write_sync() function to the DMA API which > drivers can use to explicitly force out data which may otherwise be held up > in a write buffer. It is a no-op unless and architecture provides its own > version or the function and sets ARCH_HAS_DMA_COHERENT_WRITE_SYNC. > > Signed-off-by: Mark Salter <msalter@...hat.com> > --- > Documentation/DMA-API-HOWTO.txt | 15 +++++++++++++++ > Documentation/DMA-API.txt | 12 ++++++++++++ > include/linux/dma-mapping.h | 6 ++++++ > 3 files changed, 33 insertions(+), 0 deletions(-) > > diff --git a/Documentation/DMA-API-HOWTO.txt b/Documentation/DMA-API-HOWTO.txt > index a0b6250..8c22b8b 100644 > --- a/Documentation/DMA-API-HOWTO.txt > +++ b/Documentation/DMA-API-HOWTO.txt > @@ -400,6 +400,21 @@ Make sure you've called dma_pool_free for all memory allocated > from a pool before you destroy the pool. This function may not > be called in interrupt context. > > +Some architectures which supporting DMA coherent memory may still have write > +buffering between the CPU and DMA memory. This buffering may delay CPU writes > +from reaching coherent memory in a timely manner. These delays in turn can > +lead lead to dramatic performance issues in certain cases. An architecture 'lead lead' -> 'lead' -- joshc -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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