lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [day] [month] [year] [list]
Date:	Mon, 17 Oct 2011 11:32:09 -0700 (PDT)
From:	SUJA JAMES <sujamoljames@...oo.com>
To:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Cc:	"linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>
Subject: Performance Events/Hw Cache Miss counting 

Message body
Hi All,

I am trying to query the performance management counters on my box,
which is based on Kernel 2.6.38 and running Intel processor.  I am
trying to do the same from my kernel module itself as I need to
profile my kernel modules. I use the
perf_event_create_kernel_counter() api with the following attr/config

The below  attrs/configuration is working and I am getting the counter
values/overflow_handler is getting called.
static struct perf_event_attr counter_attrs[] = {
{
      {
    .type        = PERF_TYPE_HARDWARE,
    .config        = PERF_COUNT_HW_CACHE_MISSES,
    .size        = sizeof(struct perf_event_attr),
    .pinned    = 1,
    .disabled    = 0,
    },
};

But, when I use the following attrs/config, the
perf_event_create_kernel_counter() API is failing.  Ie,
(IS_ERR(returned_pevent) is TRUE and the event is not triggered on the
CPU.  I even tried “PERF_TYPE_HARDWARE” type also with the below
config. Also I used different values for "sample_period" [100 to 1000]

static struct perf_event_attr counter_attrs[] = {
{
    .type          =  PERF_TYPE_HW_CACHE,
.config      =    PERF_COUNT_HW_CACHE_L1D               <<  0  |
              (PERF_COUNT_HW_CACHE_OP_READ           <<  8) |
            (PERF_COUNT_HW_CACHE_RESULT_MISS       << 16),
    .size      = sizeof(struct perf_event_attr),
    .pinned  = 1,
    .disabled = 0,
    },
};

Does anybody know why?. What “config” value  I should use to query the
L1D/ L1I cache misses. I think the “PERF_COUNT_HW_CACHE_MISSES” counts
only 2nd and 3rd level caches.

Thanks,
Suja

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ