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Date:	Wed, 02 Nov 2011 17:16:39 -0400
From:	Adam Jackson <ajax@...hat.com>
To:	Keith Packard <keithp@...thp.com>
CC:	Jesse Barnes <jbarnes@...tuousgeek.org>,
	intel-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
	dri-devel@...ts.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most
 places

On 11/2/11 5:13 PM, Keith Packard wrote:
> On Wed, 02 Nov 2011 16:35:51 -0400, Adam Jackson<ajax@...hat.com>  wrote:
>
>> It is?  The DP 1.1a text for lane count is "For Rev.1.1, only the
>> following three values are supported. All other values are reserved."
>
> Yeah, if you look at the MAX_LINK_RATE field, we assume that it has a
> useful value. I'll bet they were thinking of letting the spec support
> things like alternate clock rates or 3 lanes or something, and the 1.1
> version just tied things down to allow only sensible values there.
>
> How about we just always use the DPCD value?

Looks good.

Reviewed-by: Adam Jackson <ajax@...hat.com>

- ajax

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