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Message-ID: <20111110165921.GC15738@erda.amd.com>
Date:	Thu, 10 Nov 2011 17:59:21 +0100
From:	Robert Richter <robert.richter@....com>
To:	Stephane Eranian <eranian@...gle.com>
CC:	Peter Zijlstra <peterz@...radead.org>,
	<linux-kernel@...r.kernel.org>, <mingo@...e.hu>,
	<ming.m.lin@...el.com>, <ak@...ux.intel.com>
Subject: Re: [PATCH] perf_events: fix and improve x86 event scheduling

On 10.11.11 16:09:32, Stephane Eranian wrote:
> On Thu, Nov 10, 2011 at 3:37 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> > Just throwing this out there (hasn't event been compiled etc..).
> >
> > The idea is to try the fixed counters first so that we don't
> > 'accidentally' fill a GP counter with something that could have lived on
> > the fixed purpose one and then end up under utilizing the PMU that way.
> >
> > It ought to solve the most common PMU programming fail on Intel
> > thingies.

Peter, what exactly are that Intel constraints you try to solve? Could
you give a short example.

Thanks,

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center

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