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Date: Tue, 24 Jan 2012 12:20:02 +1100
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: Olof Johansson <olof@...om.net>, Arnd Bergmann <arnd@...db.de>,
<linux-arm-kernel@...ts.infradead.org>
Cc: linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
Russell King <rmk@....linux.org.uk>,
Boojin Kim <boojin.kim@...sung.com>,
Kukjin Kim <kgene.kim@...sung.com>
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-exynos/dma.c between commit 20df8641cc1a ("ARM: amba:
samsung: get rid of NO_IRQ initializers") from the arm tree and commits
2b7841baf665 ("ARM: EXYNOS: Enable MDMA driver") and bf2f272ad446 ("ARM:
EXYNOS: Support DMA for EXYNOS4X12 SoCs") from the arm-soc tree.
I fixed it up (there may be more required - see below) and can carry the
fix as necessary.
--
Cheers,
Stephen Rothwell sfr@...b.auug.org.au
diff --cc arch/arm/mach-exynos/dma.c
index 91370de,ce645ba..0000000
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@@ -69,15 -70,60 +70,47 @@@ u8 exynos4210_pdma0_peri[] =
DMACH_AC97_PCMOUT,
};
- struct dma_pl330_platdata exynos4_pdma0_pdata = {
- .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
- .peri_id = pdma0_peri,
+ u8 exynos4212_pdma0_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM2_RX,
+ DMACH_PCM2_TX,
+ DMACH_MIPI_HSI0,
+ DMACH_MIPI_HSI1,
+ DMACH_SPI0_RX,
+ DMACH_SPI0_TX,
+ DMACH_SPI2_RX,
+ DMACH_SPI2_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S2_RX,
+ DMACH_I2S2_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART2_RX,
+ DMACH_UART2_TX,
+ DMACH_UART4_RX,
+ DMACH_UART4_TX,
+ DMACH_SLIMBUS0_RX,
+ DMACH_SLIMBUS0_TX,
+ DMACH_SLIMBUS2_RX,
+ DMACH_SLIMBUS2_TX,
+ DMACH_SLIMBUS4_RX,
+ DMACH_SLIMBUS4_TX,
+ DMACH_AC97_MICIN,
+ DMACH_AC97_PCMIN,
+ DMACH_AC97_PCMOUT,
+ DMACH_MIPI_HSI4,
+ DMACH_MIPI_HSI5,
};
+ struct dma_pl330_platdata exynos4_pdma0_pdata;
+
-struct amba_device exynos4_device_pdma0 = {
- .dev = {
- .init_name = "dma-pl330.0",
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &exynos4_pdma0_pdata,
- },
- .res = {
- .start = EXYNOS4_PA_PDMA0,
- .end = EXYNOS4_PA_PDMA0 + SZ_4K,
- .flags = IORESOURCE_MEM,
- },
- .irq = {IRQ_PDMA0, NO_IRQ},
- .periphid = 0x00041330,
-};
+AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
+ {IRQ_PDMA0}, &exynos4_pdma0_pdata);
- u8 pdma1_peri[] = {
+ u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
@@@ -105,27 -151,121 +138,108 @@@
DMACH_SLIMBUS5_TX,
};
- struct dma_pl330_platdata exynos4_pdma1_pdata = {
- .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
- .peri_id = pdma1_peri,
+ u8 exynos4212_pdma1_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM1_RX,
+ DMACH_PCM1_TX,
+ DMACH_MIPI_HSI2,
+ DMACH_MIPI_HSI3,
+ DMACH_SPI1_RX,
+ DMACH_SPI1_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S1_RX,
+ DMACH_I2S1_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART1_RX,
+ DMACH_UART1_TX,
+ DMACH_UART3_RX,
+ DMACH_UART3_TX,
+ DMACH_SLIMBUS1_RX,
+ DMACH_SLIMBUS1_TX,
+ DMACH_SLIMBUS3_RX,
+ DMACH_SLIMBUS3_TX,
+ DMACH_SLIMBUS5_RX,
+ DMACH_SLIMBUS5_TX,
+ DMACH_SLIMBUS0AUX_RX,
+ DMACH_SLIMBUS0AUX_TX,
+ DMACH_SPDIF,
+ DMACH_MIPI_HSI6,
+ DMACH_MIPI_HSI7,
};
+ struct dma_pl330_platdata exynos4_pdma1_pdata;
+
-struct amba_device exynos4_device_pdma1 = {
- .dev = {
- .init_name = "dma-pl330.1",
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &exynos4_pdma1_pdata,
- },
- .res = {
- .start = EXYNOS4_PA_PDMA1,
- .end = EXYNOS4_PA_PDMA1 + SZ_4K,
- .flags = IORESOURCE_MEM,
- },
- .irq = {IRQ_PDMA1, NO_IRQ},
- .periphid = 0x00041330,
-};
+AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
+ {IRQ_PDMA1}, &exynos4_pdma1_pdata);
+ u8 mdma_peri[] = {
+ DMACH_MTOM_0,
+ DMACH_MTOM_1,
+ DMACH_MTOM_2,
+ DMACH_MTOM_3,
+ DMACH_MTOM_4,
+ DMACH_MTOM_5,
+ DMACH_MTOM_6,
+ DMACH_MTOM_7,
+ };
+
+ struct dma_pl330_platdata exynos4_mdma_pdata = {
+ .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+ .peri_id = mdma_peri,
+ };
+
+ struct amba_device exynos4_device_mdma = {
+ .dev = {
+ .init_name = "dma-pl330.2",
+ .dma_mask = &dma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &exynos4_mdma_pdata,
+ },
+ .res = {
+ .start = EXYNOS4_PA_MDMA1,
+ .end = EXYNOS4_PA_MDMA1 + SZ_4K,
+ .flags = IORESOURCE_MEM,
+ },
- .irq = {IRQ_MDMA1, NO_IRQ},
++ .irq = {IRQ_MDMA1},
+ .periphid = 0x00041330,
+ };
+
static int __init exynos4_dma_init(void)
{
if (of_have_populated_dt())
return 0;
+ if (soc_is_exynos4210()) {
+ exynos4_pdma0_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4210_pdma0_peri);
+ exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+ exynos4_pdma1_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4210_pdma1_peri);
+ exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ exynos4_pdma0_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4212_pdma0_peri);
+ exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+ exynos4_pdma1_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4212_pdma1_peri);
+ exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+ }
+
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
- amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+ amba_device_register(&exynos4_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
- amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+ amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+ dma_cap_set(DMA_MEMCPY, exynos4_mdma_pdata.cap_mask);
+ amba_device_register(&exynos4_device_mdma, &iomem_resource);
+
return 0;
}
arch_initcall(exynos4_dma_init);
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