linux-kernel - Re: [PATCH] NVMe: Fix compilation on architecturs without readq/writeq

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Date:	Thu, 02 Feb 2012 07:05:38 -0800
From:	"H. Peter Anvin" <hpa@...ux.intel.com>
To:	James Bottomley <jbottomley@...allels.com>
CC:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Ingo Molnar <mingo@...e.hu>,
	Alan Cox <alan@...rguk.ukuu.org.uk>,
	Hitoshi Mitake <h.mitake@...il.com>,
	Matthew Wilcox <matthew.r.wilcox@...el.com>,
	Roland Dreier <roland@...estorage.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] NVMe: Fix compilation on architecturs without readq/writeq

On 02/01/2012 05:05 PM, James Bottomley wrote:
>
> Incidentally, the last time this came up was with mpt fusion: for a
> write to a 64 bit register, it didn't care about order, but it did care
> about interleaving as in if you write one half of a 64 bit register and
> then write to another register, the 64 bit register effectively gets
> written with zeros in the part you didn't write to, so we had to put a
> spin lock in the open coded writeb/w/l/q() to make sure the card didn't
> get interleaved writes.
>

There are always going to be hardware which have specific needs, and for 
those open-coding makes sense, but the littleendian/bigendian pair is 
going to cover ~90% of users and make sense to can.

I worked myself on a driver (which sadly never shipped) which had an WC 
window and a UC window... the final write in a series had a completion 
bit in it and would go to the UC window after setting up a whole chunk 
of operations in the WC window (writing UC memory flushes WC memory 
ahead of it.)

Thus, the two-part breakdown of writeq() to the UC window had to write 
the low half to the WC window instead.  This is clearly not generic.

	-hpa

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