linux-kernel - Re: An extremely simplified pinctrl bindings proposal

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Mon, 06 Feb 2012 09:05:24 -1000
From:	Mitch Bradley <wmb@...mworks.com>
To:	Stephen Warren <swarren@...dia.com>
CC:	Dong Aisheng <dongas86@...il.com>,
	Shawn Guo <shawn.guo@...aro.org>,
	Dong Aisheng-B29396 <B29396@...escale.com>,
	"Linus Walleij (linus.walleij@...aro.org)" <linus.walleij@...aro.org>,
	"Sascha Hauer (s.hauer@...gutronix.de)" <s.hauer@...gutronix.de>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	"kernel@...gutronix.de" <kernel@...gutronix.de>,
	"cjb@...top.org" <cjb@...top.org>,
	"Simon Glass (sjg@...omium.org)" <sjg@...omium.org>,
	Thomas Abraham <thomas.abraham@...aro.org>,
	"Grant Likely (grant.likely@...retlab.ca)" 
	<grant.likely@...retlab.ca>,
	"ext Tony Lindgren (tony@...mide.com)" <tony@...mide.com>,
	"devicetree-discuss@...ts.ozlabs.org" 
	<devicetree-discuss@...ts.ozlabs.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: An extremely simplified pinctrl bindings proposal

I like the general approach of simplifying the pinctrl thing, as the 
previous approach did not appear to be converging.

One possible name would be "gpconfig" - for general purpose configuration.

The register access model in the strawman proposal is probably too 
simple.  32-bit memory mapped registers are certainly the most common 
subcase on ARM, but there are many other cases that occur in practice:

* Registers that must be accessed with 8, 16, or 64-bit cycles.
* Registers that have side effects on read, so read-mask-write must be 
avoided
* Registers accessed via an index/data cycle pair, thus having locking 
requirements
* Registers that must be read after being written, or otherwise 
requiring some sort of memory-ordering enforcement.
* Time delays between pairs of writes
* PCI configuration registers, which often have some combination of the 
above
* Registers behind serial buses like I2C

Both Open Firmware and ACPI have addressed this general problem.  In 
addition to a numeric identifier for the register, you need to specify 
the access semantics.  It's difficult to finitely enumerate all possible 
cases, but you can get to 99.9% with a modest number of access models, 
and then add new models as needed.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/