linux-kernel - Re: [tip:x86/urgent] x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors

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Date:	Thu, 9 Feb 2012 14:37:54 +0100
From:	Ingo Molnar <mingo@...e.hu>
To:	tip-bot for Andreas Herrmann <andreas.herrmann3@....com>
Cc:	linux-tip-commits@...r.kernel.org, linux-kernel@...r.kernel.org,
	hpa@...or.com, mingo@...hat.com, davej@...hat.com,
	Borislav.Petkov@....com, stable@...nel.org, tglx@...utronix.de
Subject: Re: [tip:x86/urgent] x86/amd: Fix L1i and L2 cache sharing
 information for AMD family 15h processors

This commit seems to cause a boot hang on an old Athlon64 CPU:

CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
numa_add_cpu cpu 0 node 0: mask now 0
ExtINT not setup in hardware but reported by MP table
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ...
..... (found apic 0 pin 0) ...
....... works.
CPU0: AMD Athlon(tm) 64 X2 Dual Core Processor 3800+ stepping 02

Thanks,

	Ingo
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