lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 09 May 2012 10:03:41 +0800
From:	Alex Shi <alex.shi@...el.com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
CC:	mgorman@...e.de, npiggin@...il.com, tglx@...utronix.de,
	mingo@...hat.com, hpa@...or.com, arnd@...db.de,
	rostedt@...dmis.org, fweisbec@...il.com, jeremy@...p.org,
	gregkh@...uxfoundation.org, glommer@...hat.com, riel@...hat.com,
	luto@....edu, avi@...hat.com, len.brown@...el.com,
	dhowells@...hat.com, fenghua.yu@...el.com, borislav.petkov@....com,
	yinghai@...nel.org, ak@...ux.intel.com, cpw@....com,
	steiner@....com, akpm@...ux-foundation.org, penberg@...nel.org,
	hughd@...gle.com, rientjes@...gle.com,
	kosaki.motohiro@...fujitsu.com, n-horiguchi@...jp.nec.com,
	paul.gortmaker@...driver.com, trenn@...e.de, tj@...nel.org,
	oleg@...hat.com, axboe@...nel.dk, kamezawa.hiroyu@...fujitsu.com,
	viro@...iv.linux.org.uk, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specific
 CPUs

On 05/08/2012 11:08 PM, Peter Zijlstra wrote:

> On Tue, 2012-05-08 at 22:03 +0800, Alex Shi wrote:
>> +void intel_tlb_flushall_factor_set(struct cpuinfo_x86 *c)
>> +{
>> +       switch (c->x86_model) {
>> +       case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
>> +               tlb_flushall_factor = 0;
>> +               break;
> 
> Why isn't this is the bottom list of core chips?


It was tested. but the bottom list cpu was not tested.

> 
>> +       case 26: /* 45 nm nehalem, "Bloomfield" */
>> +       case 30: /* 45 nm nehalem, "Lynnfield" */
>> +       case 37: /* 32 nm nehalem, "Clarkdale" */
>> +       case 44: /* 32 nm nehalem, "Gulftown" */
>> +       case 46: /* 45 nm nehalem-ex, "Beckton" */
>> +               tlb_flushall_factor = 64;
>> +               break;
>> +       case 42: /* SandyBridge */
>> +       case 45: /* SandyBridge, "Romely-EP" */
>> +               tlb_flushall_factor = 32;
>> +               break;
>> +       case 28: /* Atom */
>> +       case 47: /* 32 nm Xeon E7 */
> 
> This is a wsm-ex, right? Why isn't it listed with the other nehalems?


I don't know this. Thanks for this info

> 
>> +       case 14: /* 65 nm core solo/duo, "Yonah" */
>> +       case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
>> +       case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
>> +       case 29: /* six-core 45 nm xeon "Dunnington" */
> 
> So never use invlpg for Atom/Core/Core2?


Uh, I will remove the CPU list if they weren't tested.

> 
>> +       default:
>> +               tlb_flushall_factor = 0;
>> +       }
>> +}
> 
> 
>> @@ -364,7 +363,8 @@ flush_all:
>>                         act_entries = tlb_entries > mm->total_vm ?
>>                                         mm->total_vm : tlb_entries;
>>  
>> +                       if ((end - start)/PAGE_SIZE >
>> +                                       act_entries/tlb_flushall_factor) 
> 
> You're doing an actual full division, wouldn't a shift be better?


Thanks!

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ