linux-kernel - Re: [PATCH v2] hvc_dcc : add support to armv4 and armv5 core

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Date:	Tue, 25 Sep 2012 15:44:57 +0000
From:	Arnd Bergmann <arnd@...db.de>
To:	Matthieu CASTET <matthieu.castet@...rot.com>
Cc:	Stephen Boyd <sboyd@...eaurora.org>,
	Matthieu CASTET <castet.matthieu@...e.fr>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
	"alan@...rguk.ukuu.org.uk" <alan@...rguk.ukuu.org.uk>
Subject: Re: [PATCH v2] hvc_dcc : add support to armv4 and armv5 core

On Tuesday 25 September 2012, Matthieu CASTET wrote:
> > static inline char __dcc_getchar(void)
> > {
> >         char __c;
> > 
> >         if (__LINUX_ARM_ARCH >= 6)
> >               asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg"
> >                       : "=r" (__c));
> >       else
> >               asm volatile ("mrc p14, 0, %0, c1, c0  @ read comms data reg"
> >                       : "=r" (ret));
> >         isb();
> > 
> >         return __c;
> > }
> > 
> >       Arnd
> > 
> Yes doing that will be great!
> 
> But Alan wanted "all be runtime handled".
> 
> May be we can do something like:
> 
> 
> static int cpu_arch;
> 
> static inline char __dcc_getchar(void)
> {
>          char __c;
> 
>          if (cpu_arch >= 6)
>                 asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg"
>                         : "=r" (__c));
>         else
>                 asm volatile ("mrc p14, 0, %0, c1, c0  @ read comms data reg"
>                         : "=r" (ret));
>          isb();
> 
>          return __c;
> }

It's not possible to build a kernel that runs on ARMv5 (or below) and also on
ARMv6 (or above), so the effect would be exactly the same. While we are putting
a lot of effort into making all sorts of ARMv6 and ARMv7 based systems work
with the same kernel binary, it's highly unlikely we would ever need the
above to be runtime selected, because there are a lot of other differences
at assembly level.

	Arnd

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