linux-kernel - Re: [PATCH] dma: add new DMA control commands

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Date:	Thu, 18 Oct 2012 09:14:58 +0200
From:	Marek Vasut <marex@...x.de>
To:	Huang Shijie <b32955@...escale.com>
Cc:	Vinod Koul <vinod.koul@...ux.intel.com>, djbw@...com,
	khali@...ux-fr.org, ben-linux@...ff.org, w.sang@...gutronix.de,
	cjb@...top.org, dwmw2@...radead.org, lrg@...com,
	broonie@...nsource.wolfsonmicro.com, perex@...ex.cz, tiwai@...e.de,
	shawn.guo@...aro.org, artem.bityutskiy@...ux.intel.com,
	linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
	linux-mmc@...r.kernel.org, linux-mtd@...ts.infradead.org,
	alsa-devel@...a-project.org, linux-arm-kernel@...ts.infradead.org,
	linux@....linux.org.uk, Huang Shijie <shijie8@...il.com>,
	Fabio Estevam <fabio.estevam@...escale.com>
Subject: Re: [PATCH] dma: add new DMA control commands

Dear Huang Shijie,

Why such massive CC ?

> 于 2012年10月18日 14:18, Vinod Koul 写道:
> > Why cant you do start (prepare clock etc) when you submit the descriptor
> > to dmaengine. Can be done in tx_submit callback.
> > Similarly remove the clock when dma transaction gets completed.
> 
> I ever thought this method too.
> 
> But it will become low efficient in the following case:
> 
>    Assuming the gpmi-nand driver has to read out 1024 pages in one
> _SINGLE_ read operation.
> The gpmi-nand will submit the descriptor to dmaengine per page.

It will? Then GPMI NAND is flat our broken ... again.

> So with
> your method,
> the system will repeat the enable/disable dma clock 1024 time.

Yes, it is the driver that's wrong.

> At every
> enable/disable dma clock,
> the system has to enable the clock chain and it's parents ...
> 
> But with this patch, we only need to enable/disable dma clock one time,
> just at we select the nand chip.

You are fixing a driver problem at a framework level, wrong.

So, check how the MXS SPI driver handles descriptor chaining. Indeed, the 
Sigmatel screwed the DMA stuff good. But if you analyze the SPI driver, you'll 
notice a few important points that might come handy when you fix the GPMI NAND 
driver properly.

The direction to take here is:
1) Implement DMA chaining into the GPMI NAND driver
2) You might need to do one PIO transfer to reconfigure the IP registers between 
each segment of the DMA chain (just as MXS SPI does it)
3) You might run out of DMA descriptors when doing too long chains -- so you 
might need to fix that part of the mxs DMA driver.

> thanks
> Huang Shijie

Best regards,
Marek Vasut
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