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Date:	Fri, 16 Nov 2012 16:46:20 +0800
From:	Daniel J Blueman <daniel@...ascale-asia.com>
To:	Borislav Petkov <bp@...en8.de>
CC:	Ingo Molnar <mingo@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	H Peter Anvin <hpa@...or.com>,
	Steffen Persvold <sp@...ascale.com>, x86@...nel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3, v5] AMD64 EDAC: Add muli-domain support

On 12/11/2012 21:24, Borislav Petkov wrote:
> On Mon, Nov 05, 2012 at 02:05:24PM +0800, Daniel J Blueman wrote:
>> Fix the handling of memory controller detection to index the array
>> of detected Northbridges, allowing memory controllers over multiple
>> PCI domains in federated systems eg using Numascale's NumaConnect/
>> NumaChip.
>>
>> v4: Generate linear Northbridge ID by indexing detected Northbridges
>> v5: Reorder functions to prevent extra function declaration; merge 4th
>>      patch; simplify Fam15h code; add detail to warning
>>
>> Signed-off-by: Daniel J Blueman <daniel@...ascale-asia.com>
>
> Acked-by: Borislav Petkov <bp@...en8.de>
>
> Btw, I don't have access to a multi-socket single-board AMD system right
> now so would you please test the patchset on such a system too, if you
> haven't done so yet?
>
> Thanks a lot.

Yep, the expected memory controller indexes, population, column-strobe 
rows, banks and sysfs paths are detected on my hex-northbridge fam10h 
box with 3.7-rc5 with these patches:

EDAC MC: Ver: 3.0.0
AMD64 EDAC driver v3.4.0
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 0).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC0: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:18.2
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 1).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC1: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:19.2
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 2).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC2: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:1a.2
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 3).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC3: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:1b.2
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 4).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC4: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:1c.2
EDAC amd64: DRAM ECC enabled.
EDAC amd64: F10h detected (node 5).
EDAC MC: DCT0 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC MC: DCT1 chip selects:
EDAC amd64: MC: 0:   0MB 1:   0MB
EDAC amd64: MC: 2: 4096MB 3: 4096MB
EDAC amd64: MC: 4:   0MB 5:   0MB
EDAC amd64: MC: 6:   0MB 7:   0MB
EDAC amd64: using x8 syndromes.
EDAC amd64: MCT channel count: 2
EDAC amd64: CS2: Registered DDR3 RAM
EDAC amd64: CS3: Registered DDR3 RAM
EDAC MC5: Giving out device to 'amd64_edac' 'F10h': DEV 0000:00:1d.2
EDAC PCI0: Giving out device to module 'amd64_edac' controller 'EDAC PCI 
controller': DEV '0000:00:18.2' (POLLED)

root@...-x3755-01:/sys/devices/system/edac# ls -d mc/mc*/{rank*,csrow*}
mc/mc0/csrow2  mc/mc1/csrow2  mc/mc2/csrow2  mc/mc3/csrow2 
mc/mc4/csrow2  mc/mc5/csrow2
mc/mc0/csrow3  mc/mc1/csrow3  mc/mc2/csrow3  mc/mc3/csrow3 
mc/mc4/csrow3  mc/mc5/csrow3
mc/mc0/rank10  mc/mc1/rank10  mc/mc2/rank10  mc/mc3/rank10 
mc/mc4/rank10  mc/mc5/rank10
mc/mc0/rank11  mc/mc1/rank11  mc/mc2/rank11  mc/mc3/rank11 
mc/mc4/rank11  mc/mc5/rank11
mc/mc0/rank2   mc/mc1/rank2   mc/mc2/rank2   mc/mc3/rank2   mc/mc4/rank2 
   mc/mc5/rank2
mc/mc0/rank3   mc/mc1/rank3   mc/mc2/rank3   mc/mc3/rank3   mc/mc4/rank3 
   mc/mc5/rank3
-- 
Daniel J Blueman
Principal Software Engineer, Numascale Asia
--
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