linux-kernel - Re: [PATCH RESEND 0/5] perf: Add support for hardware breakpoint address masks

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Date:	Mon, 14 Jan 2013 11:21:35 -0600
From:	Jacob Shin <jacob.shin@....com>
To:	Jiri Olsa <jolsa@...hat.com>
CC:	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, <x86@...nel.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Stephane Eranian <eranian@...gle.com>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RESEND 0/5] perf: Add support for hardware breakpoint
 address masks

On Fri, Jan 11, 2013 at 02:54:49PM +0100, Jiri Olsa wrote:
> On Thu, Jan 10, 2013 at 02:10:54PM -0600, Jacob Shin wrote:
> > The following patchset adds address masks to existing perf hardware
> > breakpoint mechanism to allow trapping on an address range (currently
> > only single address) on supported architectures.
> 
> I haven't found any spec for that, could you please direct me?

Hello, (sorry for the late reply, was out of office on Friday)

Unfortunately, I don't have a public spec that I can share for the 
processor (AMD Family 16h) this feature first appears in yet. But once
the chip gets released sometime later, I will post a link to the 
document that will go public. Sorry .. :-(

But the patchset I think is pretty straight forward and there isn't
much more in the documentation, there are 4 MSRs (one for each DRn)
that software writes "don't care" masks (32 bits) to get the processor
to trap on range of addresses.

Thank you for taking the time to review the patchset ..

-Jacob

> 
> thanks,
> jirka
> 
> > 
> > perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> > beyond) is provided, and perf tool has been extended to do:
> > 
> >   $ perf stat -e mem:0x1000:w:0xf a.out
> >                               ^^^
> >                               "don't care" bit mask
> > 
> >   which will count writes to [0x1000 ~ 0x1010)
> > 
> > Jacob Shin (2):
> >   perf: Add hardware breakpoint address mask
> >   perf, x86: AMD implementation for hardware breakpoint address mask
> > 
> > Suravee Suthikulpanit (3):
> >   perf tools: Add breakpoint address mask to the mem event parser
> >   perf tools: Add breakpoint address mask syntax to perf list and
> >     documentation
> >   perf tools: Add breakpoint address mask test case to
> >     tests/parse-events
> > 
> >  arch/Kconfig                             |    4 ++++
> >  arch/x86/Kconfig                         |    1 +
> >  arch/x86/include/asm/cpufeature.h        |    2 ++
> >  arch/x86/include/asm/hw_breakpoint.h     |    6 ++++++
> >  arch/x86/include/asm/processor.h         |    7 ++++++
> >  arch/x86/include/uapi/asm/msr-index.h    |    6 ++++++
> >  arch/x86/kernel/cpu/amd.c                |   21 ++++++++++++++++++
> >  arch/x86/kernel/hw_breakpoint.c          |    5 +++++
> >  include/linux/hw_breakpoint.h            |    6 ++++++
> >  include/uapi/linux/perf_event.h          |    5 ++++-
> >  kernel/events/hw_breakpoint.c            |    3 +++
> >  tools/perf/Documentation/perf-record.txt |   14 ++++++++----
> >  tools/perf/tests/parse-events.c          |   34 ++++++++++++++++++++++++++++++
> >  tools/perf/util/parse-events.c           |    5 +++--
> >  tools/perf/util/parse-events.h           |    2 +-
> >  tools/perf/util/parse-events.y           |   14 ++++++++++--
> >  16 files changed, 125 insertions(+), 10 deletions(-)
> > 
> > -- 
> > 1.7.9.5
> > 
> > 
> 

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